The TLV320AIC3120 device is a low-power, highly integrated, high-performance codec which features a mono audio DAC and mono audio ADC.
The TLV320AIC3120 device features a high-performance audio codec with 24-bit mono playback and mono record functionality. The device integrates several analog features, such as a microphone interface, headphone drivers, and speaker drivers. The TLV320AIC3120 device has a fully programmable miniDSP for digital audio processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, left-justified and right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or EQ are supported by the programmable digital signal-processing blocks (PRB). An on-chip PLL provides the high-speed clock needed by the digital signal-processing block. The volume level is controlled either by pin control or by register control. The audio functions are controlled using the I2C serial bus.
The TLV320AIC3120 device is available in a 32-pin VQFN package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLV320AIC3120 | VQFN (32) | 5.00 mm × 5.00 mm |
Changes from B Revision (August 2016) to C Revision
Changes from A Revision (May 2012) to B Revision
Changes from * Revision (February 2010) to A Revision
FUNCTION | TLV320AIC3100 | TLV320AIC3110 | TLV320AIC3111 | TLV320AIC3120 |
---|---|---|---|---|
DACs | 2 | 2 | 2 | 1 |
ADCs | 1 | 1 | 1 | 1 |
Inputs / Outputs | 3/3 | 3/4 | 3/4 | 3/2 |
Resolution (Bits) | 16, 20, 24, 32 | 16, 20, 24, 32 | 16, 20, 24, 32 | 16, 20, 24, 32 |
Control Interface | I2C | I2C | I2C | I2C |
Digital Audio Interface | LJ, RJ, I2S, TDM, DSP | LJ, RJ, I2S, TDM, DSP | LJ, RJ, I2S, TDM, DSP | LJ, RJ, I2S, TDM, DSP |
Number of Digital Audio Interfaces | 1 | 1 | 1 | 1 |
Speaker Amplifier Type | Mono Differential Class-D | Stereo Differential Class-D | Stereo Differential Class-D | Mono Differential Class-D |
Configurable miniDSP | No | No | Yes | Yes |
Headphone Driver | Yes | Yes | Yes | Yes |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AVDD | 17 | - | Analog power supply |
AVSS | 16 | - | Analog ground |
BCLK | 7 | I/O | Audio serial bit clock |
DIN | 5 | I | Audio serial data input |
DOUT | 4 | O | Audio serial data output |
DVDD | 3 | - | Digital power – digital core |
DVSS | 18 | - | Digital ground |
GPIO1 | 32 | I/O | General-purpose input and output pin and multifunction pin |
HPOUT | 27 | O | Mono headphone and line driver output |
NC | 30 | O | No connection |
HPVDD | 28 | - | Headphone/line driver and PLL power |
HPVSS | 29 | - | Headphone/line driver and PLL ground |
IOVDD | 2 | - | Interface power |
IOVSS | 1 | - | Interface ground |
MCLK | 8 | I | External master clock |
MICBIAS | 12 | O | |
MIC1LM | 15 | I | Microphone/line input routed to M or P input mixer |
MIC1LP | 13 | I | Microphone/line input routed to P input mixer and left output mixer |
MIC1RP | 14 | I | Microphone/line input routed to P input mixer and left/right output mixer |
RESET | 31 | I | Device reset |
SCL | 10 | I/O | I2C control bus clock input |
SDA | 9 | I/O | I2C control-bus data input |
SPKM | 19, 23 | I/O | Cass-D speaker driver inverting output |
SPKP | 22, 26 | - | Class-D speaker driver noninverting output |
SPKVDD | 21, 24 | - | Class-D speaker driver power supply |
SPKVSS | 20, 25 | - | Class-D speaker driver power-supply ground |
VOL/MICDET | 11 | I | Volume control or microphone detection |
WCLK | 6 | I/O | Audio serial word clock |
MIN | MAX | UNIT | ||
---|---|---|---|---|
AVDD to AVSS | –0.3 | 3.9 | V | |
DVDD to DVSS | –0.3 | 2.5 | V | |
HPVDD to HPVSS | –0.3 | 3.9 | V | |
SPKVDD to SPKVSS | –0.3 | 6 | V | |
IOVDD to IOVSS | –0.3 | 3.9 | V | |
Digital input voltage | IOVSS – 0.3 | IOVDD + 0.3 | V | |
Analog input voltage | AVSS – 0.3 | AVDD + 0.3 | V | |
Operating temperature | –40 | 85 | °C | |
Junction temperature (TJ Max) | 105 | °C | ||
Storage temperature, Tstg | –55 | 150 | °C | |
Power dissipation | (TJ Max – TA) / RθJA | °C | ||
RθJA Thermal impedance (with thermal pad soldered to board) | 35 | °C/W |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
AVDD(2) | Power-supply voltage | Referenced to AVSS(1) | 2.7 | 3.3 | 3.6 | V |
DVDD | Referenced to DVSS(1) | 1.65 | 1.8 | 1.95 | ||
HPVDD | Referenced to HPVSS(1) | 2.7 | 3.3 | 3.6 | ||
SPKVDD(2) | Referenced to SPKVSS(1) | 2.7 | 5.5 | |||
IOVDD | Referenced to IOVSS(1) | 1.1 | 3.3 | 3.6 | ||
Speaker impedance | Resistance applied across class-D ouput pins (BTL) | 4 | Ω | |||
Headphone impedance | AC coupled to RL | 16 | Ω | |||
VI | Analog audio full-scale input voltage | AVDD = 3.3 V, single-ended | 0.707 | VRMS | ||
Mono line output load impedance | AC coupled to RL | 10 | kΩ | |||
MCLK(3) | Master clock frequency | IOVDD = 3.3 V | 50 | MHz | ||
SCL | SCL clock frequency | 400 | kHz | |||
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | TLV320AIC3120 | UNIT | ||
---|---|---|---|---|
RHB (VQFN) | ||||
32 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 32.7 | °C/W | |
RθJC(top) | Junction-to-case (top) thermal resistance | 23.2 | °C/W | |
RθJB | Junction-to-board thermal resistance | 6.6 | °C/W | |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W | |
ψJB | Junction-to-board characterization parameter | 6.5 | °C/W | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INTERNAL OSCILLATOR-RC_CLK | ||||||
Oscillator frequency | 8.2 | MHz | ||||
VOLUME CONTROL PIN (ADC); VOL/MICDET pin enabled | ||||||
Input voltage range | VOL/MICDET pin configured as volume control (page 0 / register 116, bit D7 = 1 and page 0 / register 67, bit D7 = 0) | 0 | 0.5 x AVDD | V | ||
Input capacitance | 2 | pF | ||||
Volume control steps | 128 | Steps | ||||
AUDIO ADC | ||||||
Microphone Input to ADC, 984-Hz Sine-Wave Input, fS = 48 kHz, AGC = OFF | ||||||
Input signal level (0-dB) | MIC with R1 = 20 kΩ (page 1 / register 48 and register 49, bits D7-D6) | 0.707 | VRMS | |||
SNR | Signal-to-noise ratio | fS = 48 kHz, 0-dB PGA gain, MIC input ac-shorted to ground; measured as idle-channel noise, A-weighted(1) (2) | 80 | 91 | dB | |
Dynamic range | fS = 48 kHz, 0-dB PGA gain, MIC input 1 kHz at –60-dBFS input applied, referenced to 0.707-VRMS input, A-weighted(1) (2) | 91 | dB | |||
THD+N | Total harmonic distortion + noise | fS = 48 kHz, 0-dB PGA gain, MIC input 1 kHz at –2 dBFS input applied, referenced to 0.707-VRMS input | –85 | –70 | dB | |
THD | Total harmonic distortion | fS = 48 kHz, 0-dB PGA gain, MIC input 1 kHz at –2 dBFS input applied, referenced to 0.707-VRMS input | –91 | dB | ||
Input capacitance | MIC input | 2 | pF | |||
Microphone Bias | ||||||
Voltage output | Page 1 / register 46, bits D1–D0 = 10 | 2.25 | 2.5 | 2.75 | V | |
Page 1 / register 46, bits D1–D0 = 01 | 2 | |||||
Voltage regulation | At 4-mA load current, page 1 / register 46, bits D1–D0 = 10 (MICBIAS = 2.5 V) | 5 | mV | |||
At 4-mA load current, page 1 / register 46, bits D1–D0 = 01 (MICBIAS = 2 V) | 7 | |||||
Audio ADC Digital Decimation Filter Characteristics | ||||||
See Section 7.3.10.4.4 for audio ADC decimation filter characteristics. | ||||||
DAC HEADPHONE OUTPUT, AC-coupled load = 16 Ω (single-ended), driver gain = 0 dB, parasitic capacitance = 30 pF | ||||||
Full-scale output voltage (0 dB) | Output common-mode setting = 1.65 V | 0.707 | VRMS | |||
SNR | Signal-to-noise ratio | Measured as idle-channel noise, A-weighted(1) (2) | 80 | 95 | dB | |
THD | Total harmonic distortion | 0-dBFS input | –85 | –65 | dB | |
THD+N | Total harmonic distortion + noise | 0-dBFS input | –82 | –60 | dB | |
Mute attenuation | 87 | dB | ||||
PSRR | Power-supply rejection ratio(4) | Ripple on HPVDD (3.3 V) = 200 mVp-p at 1 kHz | –62 | dB | ||
PO | Maximum output power | RL = 32 Ω, THD+N = –60 dB | 20 | mW | ||
RL = 16 Ω, THD+N = –60 dB | 60 | |||||
DAC LINEOUT (HP Driver in Lineout Mode) | ||||||
SNR | Signal-to-noise ratio | Measured as idle-channel noise, A-weighted | 95 | dB | ||
THD | Total harmonic distortion | 0-dBFS input, 0-dB gain | –86 | dB | ||
THD+N | Total harmonic distortion + noise | 0-dBFS input, 0-dB gain | –83 | dB | ||
DAC Digital Interpolation Filter Characteristics | ||||||
See Section 7.3.12.1.4 for DAC interpolation filter characteristics. | ||||||
DAC Output to Class-D SPEAKER OUTPUT; Load = 4 Ω (Differential), 50 pF | ||||||
Output voltage | SPKVDD = 3.6 V, BTL measurement, DAC input = 0 dBFS, CM = 1.8 V, class-D gain = 6 dB, THD = –16.5 dB | 2.3 | VRMS | |||
SPKVDD = 3.6 V, BTL measurement, DAC input = –2 dBFS, CM = 1.8 V, class-D gain = 6 dB, THD = –20 dB | 2.1 | |||||
Output, common-mode | SPKVDD = 3.6 V, BTL measurement, DAC input = mute, class-D gain = 6 dB | 1.8 | V | |||
SNR | Signal-to-noise ratio | SPKVDD = 3.6 V, BTL measurement, class-D gain = 6 dB, measured as idle-channel noise, A-weighted (with respect to full-scale output value of 2.3 VRMS)(1) (2) | 88 | dB | ||
THD | Total harmonic distortion | –65 | dB | |||
THD+N | Total harmonic distortion + noise | SPKVDD = 3.6 V, BTL measurement, DAC input = –6 dBFS, CM = 1.8 V, class-D gain = 6 dB | –63 | dB | ||
PSRR | Power-supply rejection ratio(3) | SPKVDD = 3.6 V, BTL measurement, ripple on SPKVDD = 200 mVp-p at 1 kHz | –44 | dB | ||
Mute attenuation | 110 | dB | ||||
PO | Maximum output power | SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% | 1 | W | ||
SPKVDD = 4.3 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% | 1.5 | W | ||||
SPKVDD = 5.5 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% | 2.5 | W | ||||
DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8 Ω (Differential), 50 pF | ||||||
Output voltage | SPKVDD = 3.6 V, BTL measurement, DAC input = 0 dBFS, CM = 1.8 V, class-D gain = 6 dB, THD = –16.5 dB | 2.2 | VRMS | |||
SPKVDD = 3.6 V, BTL measurement, DAC input = –2 dBFS, CM = 1.8 V, class-D gain = 6 dB, THD = –20 dB | 2.1 | VRMS | ||||
Output, common-mode | SPKVDD = 3.6 V, BTL measurement, DAC input = mute, class-D gain = 6 dB | 1.8 | V | |||
SNR | Signal-to-noise ratio | SPKVDD = 3.6 V, BTL measurement, class-D gain = 6 dB, measured as idle-channel noise, A-weighted (with respect to full-scale output value of 2.2 VRMS) | 87 | dB | ||
THD | Total harmonic distortion | SPKVDD = 3.6 V, BTL measurement, DAC input = –6 dBFS, CM = 1.8 V, class-D gain = 6 dB | –67 | dB | ||
THD+N | Total harmonic distortion + noise | SPKVDD = 3.6 V, BTL measurement, DAC input = –6 dBFS, CM = 1.8 V, class-D gain = 6 dB | –66 | dB | ||
PSRR | Power-supply rejection ratio(3) | SPKVDD = 3.6 V, BTL measurement, ripple on SPKVDD = 200 mVp-p at 1 kHz | –44 | dB | ||
Mute attenuation | 110 | dB | ||||
PO | Maximum output power | SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% | 0.7 | W | ||
SPKVDD = 4.3 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% | 1 | |||||
SPKVDD = 5.5 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB, THD = 10% | 1.6 | |||||
Output-stage leakage current for direct battery connection | SPKVDD = 4.3 V, device is powered down (power-up-reset condition) | 80 | nA | |||
ADC and DAC POWER CONSUMPTION | ||||||
For ADC and DAC power consumption based per selected processing block, see Section 7.3.9. | ||||||
DIGITAL INPUT/OUTPUT | ||||||
Logic family | CMOS | |||||
VIH | Logic Level | IIH = 5 µA, IOVDD = 1.6 V | 0.7 × IOVDD | V | ||
IIH = 5 µA, IOVDD = 1.6 V | IOVDD | |||||
VIL | IIL = 5 µA, IOVDD = 1.6 V | –0.3 | 0.3 × IOVDD | |||
IIL = 5 µA, IOVDD = 1.6 V | 0 | |||||
VOH | IOH = 2 TTL loads | 0.8 × IOVDD | ||||
VOL | IOL = 2 TTL loads | 0.1 × IOVDD | ||||
Capacitive load | 10 | pF |
Power Rating at 25°C | Derating Factor | Power Rating at 70°C | Power Rating at 85°C |
---|---|---|---|
2.3 W | 28.57 mW/°C | 1 W | 0.6 W |
PARAMETER | IOVDD = 1.1 V | IOVDD = 3.3 V | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
td(WS) | WCLK delay | 45 | 20 | ns | ||
td(DO-WS) | WCLK to DOUT delay (for LJF mode only) | 45 | 20 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay | 45 | 20 | ns | ||
ts(DI) | DIN setup | 8 | 6 | ns | ||
th(DI) | DIN hold | 8 | 6 | ns | ||
tr | Rise time | 25 | 10 | ns | ||
tf | Fall time | 25 | 10 | ns |
PARAMETER | IOVDD = 1.1 V | IOVDD = 3.3 V | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
tH(BCLK) | BCLK high period | 35 | 35 | ns | ||
tL(BCLK) | BCLK low period | 35 | 35 | ns | ||
ts(WS) | WCLK setup | 8 | 6 | ns | ||
th(WS) | WCLK hold | 8 | 6 | ns | ||
td(DO-WS) | WCLK to DOUT delay (for LJF mode only) | 45 | 20 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay | 45 | 20 | ns | ||
ts(DI) | DIN setup | 8 | 6 | ns | ||
th(DI) | DIN hold | 8 | 6 | ns | ||
tr | Rise time | 4 | 4 | ns | ||
tf | Fall time | 4 | 4 | ns |
PARAMETER | IOVDD = 1.1 V | IOVDD = 3.3 V | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
td(WS) | WCLK delay | 45 | 20 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay | 45 | 20 | ns | ||
ts(DI) | DIN setup | 8 | 8 | ns | ||
th(DI) | DIN hold | 8 | 8 | ns | ||
tr | Rise time | 25 | 10 | ns | ||
tf | Fall time | 25 | 10 | ns |
PARAMETER | IOVDD = 1.1 V | IOVDD = 3.3 V | UNIT | |||
---|---|---|---|---|---|---|
MIN | MAX | MIN | MAX | |||
tH(BCLK) | BCLK high period | 35 | 35 | ns | ||
tL(BCLK) | BCLK low period | 35 | 35 | ns | ||
ts(WS) | WCLK setup | 8 | 8 | ns | ||
th(WS) | WCLK hold | 8 | 8 | ns | ||
td(DO-BCLK) | BCLK to DOUT delay | 45 | 20 | ns | ||
ts(DI) | DIN setup | 8 | 8 | ns | ||
th(DI) | DIN hold | 8 | 8 | ns | ||
tr | Rise time | 4 | 4 | ns | ||
tf | Fall time | 4 | 4 | ns |
PARAMETER | Standard Mode | Fast Mode | UNIT | |||||
---|---|---|---|---|---|---|---|---|
MIN | TYP | MAX | MIN | TYP | MAX | |||
fSCL | SCL clock frequency | 0 | 100 | 0 | 400 | kHz | ||
tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 4 | 0.8 | μs | ||||
tLOW | LOW period of the SCL clock | 4.7 | 1.3 | μs | ||||
tHIGH | HIGH period of the SCL clock | 4 | 0.6 | μs | ||||
tSU;STA | Setup time for a repeated START condition | 4.7 | 0.8 | μs | ||||
tHD;DAT | Data hold time: for I2C bus devices | 0 | 3.45 | 0 | 0.9 | μs | ||
tSU;DAT | Data set-up time | 250 | 100 | ns | ||||
tr | SDA and SCL rise time | 1000 | 20 + 0.1Cb | 300 | ns | |||
tf | SDA and SCL fall time | 300 | 20 + 0.1Cb | 300 | ns | |||
tSU;STO | Set-up time for STOP condition | 4 | 0.8 | μs | ||||
tBUF | Bus free time between a STOP and START condition | 4.7 | 1.3 | μs | ||||
Cb | Capacitive load for each bus line | 400 | 400 | pF |