High speed analog to digital converters are notoriously sensitive to power supply noise. The most common solution to minimize that noise is to use linear power supplies, or a switch mode power supply (SMPS) from the main bus rail followed by a low droput regulator. Compared to a linear supply, there are two big advantages of being able to use a SMPS alone: the reduction in power loss and the size of the power supply. To use a SMPS alone requires careful consideration of the switching supply selected, as well as the design and layout of the SMPS to achieve the desired results of the same performance with lower power dissipation and smaller board space.

This application note uses the ADC12DJ5200 as an example of a high performance ADC where the supplies have been changed from a SMPS+LDO approach to a SMPS-only approach. This methodology can be used for many other noise sensitive applications as well. The TPS62913 low-ripple and low-noise buck converter used in this application note is specifically designed to help engineers design power supplies that meet the noise and ripple requirements for noise sensitive applications.

The ADC12DJ5200RF is a 12bit GSPS RF-analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 8GHz. ADC12DJ5200RF can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. These operating modes allow programmable tradeoffs in channel count and Nyquist bandwidth. Useable input frequency range of up to 8 GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC12DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The interface is backwards compatible with JESD204B receivers. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.

The original product evaluation module (EVM) implements low-noise LDOs in addition to the DC/DC buck regulators to minimize any impairments from the supply network. While the DC accuracy of the supply rail is specified for the ADC12DJ5200RF, there is no specification on supply voltage noise and supply voltage ripple. Any supply ripple or noise appears attenuated on the output spectrum of the ADC. This attenuation can be expressed as Power Supply Rejection Ration (PSRR) and PSRR_MOD (or PSMR) as shown in Figure 1-1.

PSRR is the attenuation of the ADC input supply ripple to the ADC output spectrum at the switching frequency fundamental of the DC-DC converter (f_DCDC). PSRR_MOD (or PSMR) is the attenuation from the ADC input to the modulated spur in the output spectrum (f_in - f_DCDC, f_in + f_DCDC).

PSRR is usually less of a concern since it is typically >40 dB and outside of the frequency of interest, however some analog rails can have PSRR of <40 dB, as shown in Figure 1-2, which shows the most sensitive supplies of the ADC12DJ5200RF are the analog supply rails of VA11 and VA19. More important is PSMR, since the attenuation from the supply rail to the modulated spur can be low for sensitive analog rails such as VA11 and VA19 on the ADC12DJ5200RF.

On the ADC12DJ5200 evaluation module, an RF PLL is used as a frequency synthesizer for clocking the ADC. Similar to high speed ADCs, higher frequencies command larger supply currents. At the same time, higher frequencies require lower clock jitter and therefore lower phase noise. Phase noise is directly impacted by the power supply noise and ripple. Since the LMX is powered from a 3.3-V supply rail, the PSRR is measured from the 3.3-V rail to the spurs of the output specturm. The LMX PSRR has a low-pass behavior with increasing attenuation at frequencies above the PLL loop bandwidth. The most sensitive frequency range for supply noise is before and around the PLL corner frequency, and heavily depends on the PLL filter characteristics. At low frequencies the noise is dominated by the external oscillator noise. Therefore, it is key to have a low-noise DC-DC converter design with <20 μV_RMS noise (100 Hz to 100 kHz) and low spectral noise density of ~0.1 uV/√(Hz) before the PLL corner frequency in the range of 1kHz to 100kHz to achieve clock jitter of 100 fs and lower. The performance of the TPS62913 is shown in Figure 1-3.

The TPS62913 has been designed specifically for low noise with the addition of an external noise reduction filter cap, which also provides the means to adjust the softstart time. Using a 470 nF C_NR/SS cap provide the noise performance desired and a 5 ms softstart time.

The TPS62912 and TPS62913 devices are a family of high-efficiency, low-noise and low-ripple synchronous buck converters. The devices are ideal for noise sensitive applications that would normally use an LDO for post regulation such as high-speed ADCs, Clock and Jitter Cleaner, Serializer, De-serializer, and Radar applications. The device operates at a fixed switching frequency of 2.2 MHz or 1 MHz, and can be synchronized to an external clock. To further reduce the output voltage ripple, the device integrates loop compensation to operate with an optional second-stage ferrite bead L-C filter. This allows an output voltage ripple below 10 µVRMS. Low-frequency noise levels, similar to a low-noise LDO, are achieved by filtering the internal voltage reference with a capacitor connected to the NR/SS pin. The optional spread spectrum modulation scheme spreads the DC/DC switching frequency over a wider span, which lowers the mixing spurs.