This user’s guide describes a power distribution network (PDN), PDN-0C, using two TPS6594-Q1 devices to supply either the DRA829V or the TDA4VM processor with independent MCU and Main power rails. DRA829/TDA4VM Dual PMIC PDN-0C enables board level isolation of the MCU safety island and main voltage resources as required for implementing two desirable features of the processor:

1. MCU processor acts as independent safety monitor (MCU Safety Island) over the Main processing resources to ensure safe system operations.
2. MCU processor maintains minimum system operations (MCU Only) to significantly reduce processor power dissipation thereby extending battery life during stand-by use cases and reducing component temperature.

The following topics are described to clarify platform system operation:

1. PDN power resource connections
2. PDN digital control connections
3. Primary and secondary PMIC static NVM contents
4. PMIC sequencing settings to support different PDN power state transitions for an advanced processor system

There are different orderable part numbers (OPNs) of the TPS6594-Q1 device available with unique NVM settings to support different end product use cases and processor types. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features (such as low power modes, processor voltages, and memory subsystems). The NVM settings can be identified by both NVM_ID and NVM_REV registers. Each PMIC device is distinguished by the part number, NVM_ID, and NVM_REV values listed in Table 2-1.

This section details how the dual TPS6594-Q1 power resources and GPIO signals are connected to the processor and other peripheral components.