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Easy-to-use evaluation board to fan out low-phase noise clocks
Simple, fast device configuration and setup
8 LP-HCSL outputs with integrated 85-Ω output terminations
8 hardware output enable (OE#) controls
Differential or single-ended input clock accepted
EVM supports all 8 differential LVDS outputs. Both output banks are available for testing by default
To quickly set up and operate the board with basic equipment, refer to the setup procedure below and test setup shown in Figure 3-1.