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  • DS90UB926Q-Q1 5- to 85-MHz, 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

    • SNLS422D July   2012  – August 2017 DS90UB926Q-Q1

      PRODUCTION DATA.  

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  • DS90UB926Q-Q1 5- to 85-MHz, 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  DC Electrical Characteristics
    6. 7.6  AC Electrical Characteristics
    7. 7.7  DC and AC Serial Control Bus Characteristics
    8. 7.8  Timing Requirements
    9. 7.9  Timing Requirements for the Serial Control Bus
    10. 7.10 Switching Characteristics
    11. 7.11 Timing Diagrams
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Speed Forward Channel Data Transfer
      2. 8.3.2  Low-Speed Back Channel Data Transfer
      3. 8.3.3  Backward-Compatible Mode
      4. 8.3.4  Input Equalization Gain
      5. 8.3.5  Common-Mode Filter Pin (CMF)
      6. 8.3.6  Video Control Signal Filter
      7. 8.3.7  EMI Reduction Features
        1. 8.3.7.1 Spread Spectrum Clock Generation (SSCG)
      8. 8.3.8  Enhanced Progressive Turnon (EPTO)
      9. 8.3.9  LVCMOS VDDIO Option
      10. 8.3.10 Power Down (PDB)
      11. 8.3.11 Stop Stream Sleep
      12. 8.3.12 Serial Link Fault Detect
      13. 8.3.13 Oscillator Output
      14. 8.3.14 Pixel Clock Edge Select (RFB)
      15. 8.3.15 Image Enhancement Features
        1. 8.3.15.1 White Balance
          1. 8.3.15.1.1 LUT Contents
          2. 8.3.15.1.2 Enabling White Balance
        2. 8.3.15.2 Adaptive HI-FRC Dithering
      16. 8.3.16 Internal Pattern Generation
      17. 8.3.17 Built-In Self Test (BIST)
        1. 8.3.17.1 BIST Configuration and Status
          1. 8.3.17.1.1 Sample BIST Sequence
        2. 8.3.17.2 Forward Channel And Back Channel Error Checking
      18. 8.3.18 I2S Receiving
        1. 8.3.18.1 I2S Jitter Cleaning
        2. 8.3.18.2 Secondary I2S Channel
          1. 8.3.18.2.1 MCLK
      19. 8.3.19 Interrupt Pin — Functional Description and Usage (INTB)
      20. 8.3.20 GPIO[3:0] and GPO_REG[8:4]
        1. 8.3.20.1 GPO_REG[8:4] Enable Sequence
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
      2. 8.4.2 Low Frequency Optimization (LFMODE)
      3. 8.4.3 Configuration Select (MODE_SEL)
      4. 8.4.4 Repeater Application
        1. 8.4.4.1 Repeater Connections
    5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Display Application
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transmission Media
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 CML Interconnect Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE
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DATA SHEET

DS90UB926Q-Q1 5- to 85-MHz, 24-Bit Color FPD-Link III Deserializer With Bidirectional Control Channel

1 Features

  • AEC-Q100 Qualified for Automotive Applications
    • Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 3B
    • Device CDM ESD Classification Level C6
    • Device MM ESD Classification Level M3
  • Bidirectional Control Interface Channel Interface With I2C-Compatible Serial Control Bus
  • Supports High-Definition (720p) Digital Video Format
  • RGB888 + VS, HS, DE and Synchronized I2S Audio Supported
  • 5- to 85-MHz PCLK Supported
  • Single 3.3-V Operation With 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
  • AC-Coupled STP Interconnect up to 10 Meters
  • Parallel LVCMOS Video Outputs
  • I2C-Compatible Serial Control Bus for Configuration
  • DC-Balanced and Scrambled Data With Embedded Clock
  • Adaptive Cable Equalization
  • Supports Repeater Application
  • @ SPEED Link BIST Mode and LOCK Status Pin
  • Image Enhancement (White Balance and Dithering) and Internal Pattern Generation
  • EMI Minimization (SSCG and EPTO)
  • Low Power Modes Minimize Power Dissipation
  • Backward-Compatible With FPD-Link II

2 Applications

  • Automotive Display for Navigation
  • Rear Seat Entertainment Systems
  • Automotive Drive Assistance
  • Automotive Megapixel Camera Systems

3 Description

The DS90UB926Q-Q1 deserializer, in conjunction with the DS90UB925Q-Q1 serializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image-sensing applications.

This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UB926Q-Q1 deserializer recovers the RGB data, three video control signals, and four synchronized I2S audio signals. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UB926Q-Q1 WQFN (60) 9.00 mm × 9.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Display System Diagram

DS90UB926Q-Q1 30143427.gif

4 Revision History

Changes from C Revision (February 2017) to D Revision

  • Reverted all previous MLCK content changes made in Revision C back to Revision BGo
  • Deleted the disable I2S jitter cleaner noteGo

Changes from B Revision (January 2015) to C Revision

  • Changed pin 60 from MCLK to RES2 Go
  • Changed MCLK to RES2 Go
  • Added note to disable I2S jitter cleaner Go
  • Changed MCLK to RES2 Go
  • Deleted reference to MCLK in this section Go
  • Deleted reference to MCLK in this section Go
  • Deleted reference to MCLKGo
  • Changed MCLK section Go
  • Changed MCLK columns of Audio Interface Frequencies table Go
  • Changed the values in columns 2 through 5 in Configuration Select (MODE_SEL) tableGo
  • Changed the values in columns 2 to 5 in Serial Control Bus Addresses for IDx tableGo
  • Changed register reference to MCLK Go
  • Changed Typical Display System Diagram (removed reference to MCLK) Go
  • Changed wording of Power Up Requirements and PDB Pin subsection and added Power-Up Sequence graphicGo

Changes from A Revision (April 2013) to B Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

Changes from * Revision (July 2012) to A Revision

  • Corrected typo in table “DC and AC Serial Control Bus Characteristics” from VDDIO to VDD33, added “Note: BIST is not available in backwards compatible mode.”, added Recommended FRC settings table, changed entire layout of Data Sheet to TI format, added to Absolute Maximum Rating section, note (3): The maximum limit (VDDIO +0.3V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning from HIGH to LOW), deleted derate from Maximum Power Dissipation Capacity at 25°C.Go
  • "Note: BIST is not available in backwards compatible mode."Go

5 Description (continued)

The DS90UB926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data.

An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features.

 
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