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  • DS125DF111 Multi-Protocol 2-Channel 9.8 - 12.5 Gb/s Retimer

    • SNLS450A January   2014  – June 2015 DS125DF111

      PRODUCTION DATA.  

  • CONTENTS
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  • DS125DF111 Multi-Protocol 2-Channel 9.8 - 12.5 Gb/s Retimer
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration And Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
        1. 7.3.1.1 Input Channel Equalization
        2. 7.3.1.2 Clock and Data Recovery
        3. 7.3.1.3 PRBS Pattern Generator
        4. 7.3.1.4 Datapath Multiplexer and Output Driver
        5. 7.3.1.5 Reference Clock
        6. 7.3.1.6 Control Pins
          1. 7.3.1.6.1 Pin Mode Limitation
        7. 7.3.1.7 Eye Opening Monitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 Control Pin Mode
      2. 7.4.2 SMBus Master Mode and SMBus Slave Mode
    5. 7.5 Programming
      1. 7.5.1 SMBus Interface
        1. 7.5.1.1  Address Lines
        2. 7.5.1.2  Device Configuration in SMBus Slave Mode
        3. 7.5.1.3  Bit Fields in the Register Set
        4. 7.5.1.4  Writing To and Reading from the Control/Shared Registers
        5. 7.5.1.5  SMBus Strap Observation
        6. 7.5.1.6  Interrupt Channel Flag Bits
        7. 7.5.1.7  Control/Shared Register Reset
        8. 7.5.1.8  Device Revision and Device ID
        9. 7.5.1.9  Channel Select Register
        10. 7.5.1.10 Resetting Individual Channels of the Retimer
        11. 7.5.1.11 Rate and Subrate Setting
        12. 7.5.1.12 Overriding the CTLE Boost Setting
        13. 7.5.1.13 Overriding the Output Multiplexer
        14. 7.5.1.14 Overriding the VCO Divider Selection
        15. 7.5.1.15 Using the Internal Eye Opening Monitor
        16. 7.5.1.16 Overriding the DFE Tap Weights and Polarities
        17. 7.5.1.17 Enabling Slow Rise/Fall Time on the Output Driver
        18. 7.5.1.18 Using the PRBS Generator
        19. 7.5.1.19 Inverting the Output Polarity
        20. 7.5.1.20 Figure of Merit Adaption
        21. 7.5.1.21 Setting the Rate and Subrate for Lock Acquisition
        22. 7.5.1.22 Setting the Adaption/Lock Mode
        23. 7.5.1.23 Initiating Adaption
        24. 7.5.1.24 Overriding the CTLE Settings Used for CTLE Adaption
        25. 7.5.1.25 Setting the Output Differential Voltage
        26. 7.5.1.26 Setting the Output De-Emphasis Setting
        27. 7.5.1.27 CTLE Setting for Divide by 4 and Divide by 8 VCO Ranges
    6. 7.6 Register Maps
      1. 7.6.1 Reading To and Writing from the Channel Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
        1. 8.2.3.1 SFF-8431 Testing
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
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DATA SHEET

DS125DF111 Multi-Protocol 2-Channel 9.8 - 12.5 Gb/s Retimer

1 Features

  • Pin Compatible Retimer Family
    • DS110DF111 with DFE: 8.5 - 11.3 Gbps
    • DS125DF111 with DFE: 9.8 - 12.5 Gbps
  • Adaptive CTLE: 33 dB Max Boost at 6.25 GHz
  • Self Tuning 5-Tap DFE
  • Raw Equalized and Retimed Data Loopback
  • Adjustable Transmit VOD: 600 to 1300 mVp-p
  • Settable Tx De-Emphasis Driver 0 to –12dB
  • Low Power Consumption: 220 mW/Channel
  • Locks to Half/Quarter/Eighth Data Rates for Legacy Support
  • On-Chip Eye Monitor (EOM), PRBS Generator
  • Input Signal Detection, CDR Lock Detection/Indicator
  • Single 3.3-V or 2.5-V Power Supply
  • SMBus, EEPROM, or Pin Based Configuration
  • 4-mm x 4-mm, 24-Pin WQFN Package
  • Operating Temp Range: –40°C to 85°C

2 Applications

  • Front Port Optical Interconnects
  • SFF-8431
  • 10G/1G Ethernet
  • CPRI

3 Description

The DS125DF111 is a dual channel (1-lane bidirectional) retimer with integrated signal conditioning. The DS125DF111 includes an input Continuous-Time Linear Equalizer (CTLE), clock and data recovery (CDR) and transmit driver on each channel.

The DS125DF111 with its on-chip Decision Feedback Equalizer (DFE) can enhance the reach and robustness of long, lossy, cross-talk-impaired high speed serial links to achieve BER < 1x10–15. For less demanding applications/interconnects, the DFE can be switched off and achieve the same BER performance. The DS125DF111 and DS110DF111 devices are pin-compatible.

Each channel of the DS125DF111 independently locks to specific serial data at data rates from 9.8 to 12.5 Gbps or to any supported sub-rate of these data rates. This simplifies system design and lowers overall cost.

Programmable transmit de-emphasis driver offers precise settings to meet the SFF-8431 output eye template. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnect and backplanes with multiple connectors. The CDR function is ideal for use in front port parallel optical module applications to reset the jitter budget and retime high speed serial data.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS125DF111 WQFN (24) 4.0 mm × 4.0 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Typical Application

DS125DF111 SimplifiedSchematic_125_r1.gif

4 Revision History

Changes from * Revision (January 2014) to A Revision

  • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Pin Configuration And Functions

RTW Package
24-Pin WQFN
Top View
DS125DF111 3420725.gif

Pin Functions

PIN I/O TYPE DESCRIPTION
NAME NO.
HIGH SPEED DIFFERENTIAL I/OS
OUTA± 7, 8 O, CML Inverting and non-inverting CML-compatible differential outputs.
Outputs require AC coupling
OUTB± 20, 19 O, CML Inverting and non-inverting CML-compatible differential outputs.
Outputs require AC coupling
INA± 24, 23 I, CML Inverting and non-inverting CML-compatible differential inputs. An on-chip 100 Ω terminating resistor connects INA+ to INA-
Inputs require AC coupling. TI recommends 100 nF capacitors. Note that for SFP+ applications, AC coupling is included as part of the SFP+ module.
INB± 11, 12 I, CML Inverting and non-inverting CML-compatible differential inputs. An on-chip 100 Ω terminating resistor connects INB+ to INB-
Inputs require AC coupling. TI recommends 100 nF capacitors. Note that for SFP+ applications, AC coupling is included as part of the SFP+ module.
LOOP FILTER CONNECTION PIN
LPF_CP_A, LPF_REF_A 2, 1 I/O, analog Loop filter connection, place a 22 nF ± 10% capacitor in series between LPF_CP_A and LPF_REF_A
LPF_CP_B, LPF_REF_B 17, 18 I/O, analog Loop filter connection, place a 22 nF ± 10% capacitor in series between LPF_CP_B and LPF_REF_B
REFERENCE CLOCK I/O
REFCLK_IN 14 I, LVCMOS 25 MHz ± 100 ppm clock from external Oscillator
INDICATOR PINS
LOCK 16 O, LVCMOS LOCK VOH is referenced to VIN voltage level. Note that this pin is shared with strap input functions read at startup. The Address value loaded into pin 16 (ADDR0) at startup changes the definition of the LOCK pin output. See the Shared Register Definition in Table 7 for more details.
LOS/INT# 13 O, Open Drain Output is driven LOW when a valid signal is present on INA. Output is released when signal on INA is lost (LOS). This output can be redefined as an INT# signal which will be driven LOW for any of the following conditions.(2)
1. The EOM check returns a value below the HEO/VEO interrupt threshold.
2. CDR check returns lock/loss status.
3. Signal Detector returns detect/loss status.
SMBus MODE PINS
ENSMB 3 I, 4-Level System Management Bus (SMBus) enable pin
HIGH = Register Access, SMBus Slave mode
FLOAT = SMBus Master read from External EEPROM
20 K to GND = Reserved
LOW = External Pin Control Mode. See section on Pin Mode Limitation
SDA 4 I, SMBus
O, Open Drain		 Data Input / Open Drain Output
External pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant(2)
SCL 5 I, SMBus
O, Open Drain		 Clock input in SMBus slave mode. Can also be an open drain output in SMBus master mode
Pin is 3.3 V LVCMOS Tolerant(2)
TX_DIS 6 I, 4-Level Disable the OUTB transmitter
HIGH = OUTA Enabled/OUTB Disabled
FLOAT = Reserved
20 K to GND = Reserved
LOW = OUTA/OUTB Enabled (normal operation)
ADDR0 16 I, LVCMOS This pin sets the SMBus address for the retimer.
This pin is a strap input. The state is read on power-up to set the SMBus address in SMBus control mode. The latched value of ADDR0 read at startup will change the LOCK output definition. See the Shared Register Definition in Table 7 for more details.(3)
ADDR1/DONE# 10 IO, LVCMOS This pin sets the SMBus address for the retimer in SMBus Slave Mode.
DONE#. VOH is referenced to VIN voltage level. DONE# goes low to indicate that the SMBus master EEPROM read has been completed in SMBus Master Mode(3)
READEN# 9 I, LVCMOS Initiates SMBus master EEPROM read. When multiple DS125DF111 are connected to a single EEPROM, the READEN# input can be daisy chained to the DONE# output. In SMBus Slave Mode this pin should be tied to Logic 0. (4)
PIN CONTROL (ENSMB = LOW) (1)
DEMA 4 I, 4-Level Set CHA output de-emphasis level in pin control mode (4)
DEMB 5 I, 4-Level Set CHB output de-emphasis level in pin control mode (4)
LPBK 6 I, 4-Level HIGH = INA goes to OUTA, INB goes to OUTB
FLOAT = INB goes to OUTA and OUTB
20 K to GND = INA goes to OUTA and OUTB
LOW = INA goes to OUTB, INB goes to OUTA(4)
VODA 9 I, 4-Level Set CHA output launch amplitude in pin control mode (4).
VODB 10 I, 4-Level Set CHB output launch amplitude in pin control mode(4)
POWER
VDD 21, 22 Power VDD = 2.5 V ± 5%. See Figure 12.
3.3-V supply mode: VDD = 2.5 V is supplied the internal output regulator. Pins only require de-coupling caps; no external supply is needed.
2.5-V supply mode: VDD input = 2.5 V ± 5%.
VIN 15 Power Regulator Input (4)with Integrated Supply Mode Control. See Figure 12.
3.3-V supply mode: VIN input = 3.3 V ± 10%.
2.5-V Mode Operation: VIN Supply Input = 2.5 V ± 5%. Connect directly to VDD supply pins.
DAP PAD Power GND reference
The exposed pad at the center of the package must be connected to ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package
(1) When in pin control mode, the DS125DF111 device operates at 12.288, 9.8304, 6.144, 4.9152, 3.072, 2.4576, 1.536, or 1.2288 Gbps and has limited VOD and De-Emphasis control. See Table 9.
(2) The LOS/INT# pin is an open drain output which requires external pull-up resistor (typically connected to 2.5 V or 3.3 V for system logic compatibility) to achieve a HIGH level.
(3) This pin is shared with other functions.
(4) This pin is shared with other functions.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Supply Voltage (VDD) –0.5 2.75 V
Supply Voltage (VIN) –0.5 4 V
LVCMOS Input/Output Voltage –0.5 4 V
4-Level Input Voltage (2.5-V mode) –0.5 2.75 V
4-Level Input Voltage (3.3-V mode) –0.5 4 V
SMBus Input/Output Voltage –0.5 4 V
CML Input Voltage –0.5 VDD + 0.5 V
CML Input Current –30 30 mA
Storage temperature, Tstg –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions.
(2) Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For soldering specifications, see product folder at SNOA549.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±3000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM(1) MAX UNIT
Supply Voltage 2.5 V Mode 2.375 2.5 2.625 V
3.3 V Mode 3 3.3 3.6
Ambient Temperature –40 25 +85 °C
SMBus (SDA, SCL) Pull-up Supply Voltage 2.7 3.3 3.6 V

6.4 Thermal Information

THERMAL METRIC(1) DS125DF111 UNIT
RTW (WQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 35 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34 °C/W
RθJB Junction-to-board thermal resistance 13.4 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 13.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
R_Baud Input baud rate (primary VCO range) Full Rate: DS125DF111 9.8 12.5 Gbps
R_Baud2 Divide by 2 Half Rate: DS125DF111 4.9 6.25 Gbps
R_Baud4 Divide by 4 Quarter Rate: DS125DF111 2.45 3.125 Gbps
R_Baud8 Divide by 8 Eighth Rate: DS125DF111 1.225 1.5625 Gbps
FSDC SMBus Clock Rate Slave Mode Clock Rate 100 400 kHz
Master Mode Clock Rate 280 400 520
REFCLK Reference Clock Rate ± 100 ppm 25 MHz
DCREFCLK Reference Clock Duty Cycle 40% 50% 60%
POWER SUPPLY CURRENT
IDD DS125DF111 Current Consumption
(Whole Device)		 Average Supply Current, Default Settings, CHA and CHB Locked
DFE Enabled		 175 mA
Average Supply Current, CHA and CHB Locked
Default Settings except DFE Disabled		 155 mA
Maximum Transient Supply Current Default Settings: CHA and CHB valid input signal detected
CHA and CHB acquiring LOCK(2)		 294 333 mA
NTps Supply Noise Tolerance 50 Hz to 100 Hz 100 mVp-p
100 Hz to 10 MHz 40 mVp-p
10 MHz to 3.0 GHz 10 mVp-p
LVCMOS (ADDR[1:0], READEN#, REFCLK_IN, DONE#, LOCK)
VIH High level input voltage 2.5 V or 3.3 V Supply Mode 1.7 VIN V
VIL Low level input voltage 2.5 V or 3.3 V Supply Mode 0.7
VOH1 High level output voltage IOH = -3 mA 2 VIN V
VOH2 High level output voltage IOH = –100 µA VIN - 0.1
VOL Low level output voltage IOL = 3 mA 0.4
IIN Input leakage current VINPUT = GND or VIN –15 15 µA
4-LEVEL INPUTS (ENSMB, DEMA, DEMB, LPBK, TX_DIS, VODA, VODB)
IIH-R Input leakage current High VINPUT = VIN 80 µA
IIL-R Input leakage current Low VINPUT = GND –160 µA
OPEN DRAIN (LOS/INT#)
VOL Low level output voltage IOL = 3 mA 0.4 V
SIGNAL DETECT
SDH Signal Detect:
ON Threshold Level		 Default level to assert
Signal Detect, 12.5 Gbps, PRBS31		 18 mVp-p
SDL Signal Detect:
OFF Threshold Level		 Default level to de-assert
Signal Detect, 12.5 Gbps, PRBS31		 14 mVp-p
CML RX INPUTS
R_Rd DC Input differential Resistance 80 100 120 Ω
RLRX-IN Input Return-Loss SDD11 10 MHz –19 dB
SDD11 2.0 GHz –13
SDD11 6.0 - 11.1 GHz -8
VRX-LAUNCH Source Transmit Signal Level Tx Launch amplitude of driver connected to DS125DF111 inputs(3) 1600 mVp-p
TRANSMIT JITTER SPECS(4)
TTJ Total Jitter (@ BER = 1E-12) PRBS7, 9.8304 Gbps 7.5 ps
TRJ Random Jitter PRBS7, 9.8304 Gbps 0.33 ps (RMS)
TDJ Deterministic Jitter PRBS7, 9.8304 Gbps 3.6 ps
CLOCK AND DATA RECOVERY
BWPLL PLL Bandwidth -3 dB Measured at 12.5 Gbps, 0.4 UI Sj Injection 3.9 MHz
JTOL Total jitter tolerance Jitter per SFF-8431 Appendix D.11
Combination of Dj, Pj, and Rj		 > 0.7 UI
TLOCK1 CDR Lock Time Best Lock Time 9.8304 Gbps
Adapt Mode 0 (Register 0x31[6:5])
CTLE Set - no Auto adapt
Disable HEO/VEO Lock Monitor - (Register 0x3E[7])
HEO/VEO thresholds set to 0 - (Register 0x6A[7:0])
Rate/Subrate limited to single divide ratio. See Table 9
CDR Reset and Release - (Register 0x0A[3:2])
Signal Detect Preset and Release - Before input signal is present (Register 0x14[7:6])		 1.3 ms
TLOCK2 CDR Lock Time Standards Based, 9.8304 Gbps, Default settings(5) 35 ms
TEMPLOCK CDR Lock Lock Temperature Range
–40°C to 85°C operating range
 125 °C
(1) Typical values represent the most likely parametric norm as determined at the time of design and characterization. Actual typical values may vary over time and will also depend on the application and configuration.
(2) Peak current only occurs during lock acquisition, limit is for power supply design not needed for thermal calculations.
(3) DS125DF111 equalizer is optimized to adapt to Tx Launch amplitudes between 600 - 1200 mV. Amplitudes above or below this range will reduce the overall equalizer performance.
(4) Rj and Dj Jitter decomposition as reported by TEK DSA8200 Sampling scope using a 80E09 Electrical sampling module, 80A06 Pattern trigger, and 82A04 Phase Reference Module.
(5) The typical LOCK time can vary based on data-rate, input channel, and specific DS125DF111 settings.
(6) EEPROM interface requires 520 kHz capable EEPROM device.

6.6 Timing Requirements

MIN NOM MAX UNIT
CML TX OUTPUTS
T_VDIFF0 Output differential voltage Default setting, 8T pattern 400 550 675 mVp-p
T_VDIFF7 Output differential voltage Maximum setting, 8T pattern
Requires SMBus Control		 1000 1200 mVp-p
VOD_DE De-emphasis Level Maximum setting, VOD and DE
Requires SMBus Control
Input: 9.8304 Gbps, 16T pattern		 –12 dB
T_Rd DC Output Differential Resistance 100 Ω
TR/TF Output Rise/Fall Time Full Slew Rate (Channel Reg 0x18[2] = 0), minimum VOD
20% - 80%, See Figure 1.
Input: 9.8304 Gbps, 8T Pattern		 36 ps
TRS/TFS Output Rise/Fall Time Limited Slew Rate (Channel Reg 0x18[2] = 1), minimum VOD
20% - 80%, See Figure 1.
Input: 9.8304 Gbps, 8T Pattern		 50 ps
TSDD22 Output differential mode return loss SDD22 10 MHz - 2.0 GHz –18 dB
SDD22 5.5 GHz –11
SDD22 6 - 11.1 GHz –9
TPD Propagation Delay Retimed Data: 9.8304 Gbps,
See Figure 2.		 1.5UI + 200ps ps
TPD-RAW Propagation Delay Raw Data: 9.8304 Gbps,
See Figure 2.		 200 ps
SERIAL BUS INTERFACE CHARACTERISTICS(6) See Figure 3.
VIL Data, Clock Input Low Voltage
(SDA / SCL)		 0.8 V
VIH Data, Clock Input High Voltage
(SDA / SCL)		 2.1 3.6 V
VOL Output Low Voltage SDA or SCL, IOL = 1.25 mA 0 0.36 V
TR SDA Rise Time, Read Operation SDA, RPU = 4.7 K, Cb < 50 pF 140 ns
TF SDA Fall Time, Read Operation SDA, RPU = 4.7 K, Cb < 50 pF 60 ns
TSU;DAT Setup Time, Read Operation 560 ns
THD;DAT Hold Time, Read Operation 615 ns
CIN Input Capacitance SDA or SCL < 5 pF
TR SCL and SDA, Rise Time 300 ns
TF SCL and SDA, Rise Time 1000 ns
DS125DF111 risefall.gifFigure 1. Differential Output Edge Rate
DS125DF111 30201603.gifFigure 2. Differential Propagation Delay
DS125DF111 30201605.gifFigure 3. SMBus Timing Diagram

6.7 Typical Characteristics

DS125DF111 degain.gif
Test Conditions
Datarate: 10.3125 Gbps with a PRBS7 pattern
VOD Setting: 1000mV
Temperature: 25°C and VDD = 2.5V
Figure 4. De-Emphasis Gain vs. Frequency
DS125DF111 eye.png
Jitter Measurements
Rj (RMS): 315 fs Dj: 3.74 ps Tj (1E-12): 7.33 ps
Figure 5. Output Eye Diagram 10.3125 Gbps

 
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