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The LMR16020 is a 60 V, 2 A SIMPLE SWITCHER® step down regulator with an integrated high-side MOSFET. With a wide input range from 4.3 V to 60 V, it’s suitable for various applications from industrial to automotive for power conditioning from unregulated sources. The regulator’s quiescent current is 40 µA in Sleep-mode, which is suitable for battery powered systems. An ultra-low 1 μA current in shutdown mode can further prolong battery life. A wide adjustable switching frequency range allows either efficiency or external component size to be optimized. Internal loop compensation means that the user is free from the tedious task of loop compensation design. This also minimizes the external components of the device. A precision enable input allows simplification of regulator control and system power sequencing. The device also has built-in protection features such as cycle-by-cycle current limit, thermal sensing and shutdown due to excessive power dissipation, and output overvoltage protection.
The LMR16020 is available in an 8-pin HSOIC package with exposed pad for low thermal resistance.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMR16020PDDAR | HSOIC (8) | 4.89 mm x 3.90 mm |
Changes from * Revision (December 2015) to A Revision
PIN | TYPE (1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BOOT | 1 | P | Bootstrap capacitor connection for high-side MOSFET driver. Connect a high quality 0.1 μF capacitor from BOOT to SW. |
VIN | 2 | P | Connect to power supply and bypass capacitors CIN. Path from VIN pin to high frequency bypass CIN and GND must be as short as possible. |
EN | 3 | A | Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float or connect to VIN to enable. Adjust the input under voltage lockout with two resistors. See the Enable and Adjusting Under voltage lockout section. |
RT/SYNC | 4 | A | Resistor Timing or External Clock input. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to frequency programming by resistor. |
FB | 5 | A | Feedback input pin, connect to the feedback divider to set VOUT. Do not short this pin to ground during operation. |
PGOOD | 6 | A | Power-Good pin, open drain output for power-good flag, use a 10 kΩ to 100 kΩ pull-up resistor to logic rail or other DC voltage no higher than 7 V. |
GND | 7 | G | System ground pin. |
SW | 8 | P | Switching output of the regulator. Internally connected to high-side power MOSFET. Connect to power inductor. |
Thermal Pad | 9 | G | Major heat dissipation path of the die. Must be connected to ground plane on PCB. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input Voltages | VIN, EN to GND | -0.3 | 65 | V |
BOOT to GND | -0.3 | 71 | ||
FB to GND | -0.3 | 7 | ||
RT/SYNC to GND | -0.3 | 3.6 | ||
PGOOD to GND | -0.3 | 7 | ||
Output Voltages | BOOT to SW | 6.5 | V | |
SW to GND | -3 | 65 | ||
TJ | Junction temperature | -40 | 150 | °C |
Tstg | Storage temperature | -65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM)(1) | ±2000 | V |
Charged-device model (CDM) (2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Buck Regulator | VIN | 4.3 | 60 | V |
VOUT | 0.8 | 50 | ||
BOOT | 66 | |||
SW | -1 | 60 | ||
FB | 0 | 5 | ||
Control | EN | 0 | 60 | V |
RT/SYNC | 0 | 3.3 | ||
PGOOD to GND | 0 | 5 | ||
Frequency | Switching frequency range at RT mode | 200 | 2500 | kHz |
Switching frequency range at SYNC mode | 250 | 2300 | ||
Temperature | Operating junction temperature, TJ | -40 | 125 | °C |
THERMAL METRIC (1) (2) | LMR16020 | UNIT | |
---|---|---|---|
DDA (HSOIC) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 42.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 9.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 25.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 56.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 25.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY (VIN PIN) | ||||||
VIN | Operation input voltage | 4.3 | 60 | V | ||
UVLO | Under voltage lockout thresholds | Rising threshold | 3.8 | 4.0 | 4.2 | V |
Hysteresis | 285 | mV | ||||
ISHDN | Shutdown supply current | VEN = 0 V, TA = 25 °C, 4.3 V ≤ VIN ≤ 60 V | 1.0 | 3.0 | μA | |
IQ | Operating quiescent current (non- switching) | VFB = 1.0 V, TA = 25 °C | 40 | μA | ||
ENABLE (EN PIN) | ||||||
VEN_TH | EN Threshold Voltage | 1.05 | 1.20 | 1.38 | V | |
IEN_PIN | EN PIN current | Enable threshold +50 mV | -4.6 | μA | ||
Enable threshold -50 mV | -1.0 | |||||
IEN_HYS | EN hysteresis current | -3.6 | μA | |||
SOFT-START | ||||||
tSS | Internal soft-start time | 10% to 90% of FB voltage | 4.0 | ms | ||
POWER GOOD (PGOOD PIN) | ||||||
VPG_UV | Power-good flag under voltage tripping threshold | POWER GOOD (% of FB voltage) | 94 | % | ||
POWER BAD (% of FB voltage) | 92 | % | ||||
VPG_OV | Power-good flag over voltage tripping threshold | POWER BAD (% of FB voltage) | 109 | % | ||
POWER GOOD (% of FB voltage) | 107 | % | ||||
VPG_HYS | Power-good flag recovery hysteresis | % of FB voltage | 2 | % | ||
IPG | PGOOD leakage current at high level output | VPull-Up = 5 V | 10 | 200 | nA | |
VPG_LOW | PGOOD low level output voltage | IPull-Up = 1 mA | 0.1 | V | ||
VIN_PG_MIN | Minimum VIN for valid PGOOD output | VPull-Up < 5 V at IPull-Up = 100 μA | 1.6 | 1.95 | V | |
VOLTAGE REFERENCE (FB PIN) | ||||||
VFB | Feedback voltage | TJ = 25 °C | 0.746 | 0.750 | 0.754 | V |
TJ = -40 °C to 125 °C | 0.735 | 0.750 | 0.765 | V | ||
HIGH-SIDE MOSFET | ||||||
RDS_ON | On-resistance | VIN = 12 V, BOOT to SW = 5.8 V | 155 | 320 | mΩ | |
High-side MOSFET CURRENT LIMIT | ||||||
ILIMT | Current limit | VIN = 12 V, TA = 25 °C, Open Loop | 2.5 | 3.15 | 3.8 | A |
THERMAL PERFORMANCE | ||||||
TSHDN | Thermal shutdown threshold | 170 | °C | |||
THYS | Hysteresis | 12 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSW | Switching frequency | RT = 11.5 kΩ | 1758 | 1912 | 2066 | kHz |
Switching frequency range at SYNC mode | 250 | 2300 | ||||
VSYNC_HI | SYNC clock high level threshold | 1.7 | V | |||
VSYNC_LO | SYNC clock low level threshold | 0.5 | ||||
TSYNC_MIN | Minimum SYNC input pulse width | Measured at 500 kHz, VSYNC_HI > 3 V, VSYNC_LO < 0.3 V | 30 | ns | ||
TLOCK_IN | PLL lock in time | Measured at 500 kHz | 100 | µs | ||
TON_MIN | Minimum controllable on time | VIN = 12 V, BOOT to SW = 5.8 V, ILoad = 1 A | 90 | ns | ||
DMAX | Maximum duty cycle | fSW = 200 kHz | 97% |
VOUT = 3.3 V | fSW = 500 KHz |
VOUT = 5 V | fSW = 500 KHz |
VOUT = 5 V | fSW = 500 KHz |
VOUT = 3.3 V | fSW = 500 KHz |
VIN = 12 V |
VOUT = 3.3 V | fSW = 500 KHz |
VOUT = 5 V | fSW = 500 KHz |
VOUT = 5 V | fSW = 500 KHz |
IOUT = 0 A |