At the center of every application is the need for memory. With limited on-chip processor memory, external memory serves as a solution for large software systems and data storage, and an unstable external memory interface can result in system failures or hinder software development. To prevent potential system level anomalies and ensure robust systems, hardware must be configured correctly and tested thoroughly.
The Jacinto 7 DDRSS Register Configuration Tool focuses on post layout activities, and provides a simplified solution to configure the Texas Instruments (TI) Jacinto 7 processors for accessing the specific double data rate (DDR) memory part number that is selected for a system. This document provides a detailed description on how to use the associated application files to generate appropriate register settings for a unique system and memory component, updating the source code of supported software development kits (SDKs), and address common questions or issues that may arise. The document introduction provides a complete list of processors and memory types supported by the Jacinto 7 DDRSS Register Configuration Tool.
The spreadsheet discussed in this document can be downloaded from the following URL: https://www.ti.com/lit/zip/spracu8.
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The Jacinto™ 7 DDRSS Register Configuration Tool provides a simplified solution to configuring the Texas Instruments Jacinto 7 processors for accessing DDR memories. The tool consists of this document and a corresponding spreadsheet that generates register settings based on user input. The output of the spreadsheet is intended to be easily integrated with the supporting DDR drivers provided with the software development kits available for each supported processor.
This document provides details pertaining to the features of the tool, as well as steps outlining the procedure to utilize the spreadsheet and update software accordingly.
The key supported and unsupported features of the Jacinto 7 DDRSS Register Configuration Tool are provided in the lists shown in Section 1.1.1 and Section 1.1.2.