SPRACY7 October 2021 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
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The Embedded Pattern Generator (EPG) module is a customizable pattern and clock generator that could serve many test and application scenarios that require a simple pattern generator or a periodic clock generator. The EPG module can also be used to capture an incoming serial stream of data. The EPG module allows users to design new clock generators,pulse width modulators (PWMs), serial communication modules, and so forth.
The EPG module can be used as an independent peripheral or it can be used along side other peripherals such as CAN. When used alongside other peripherals, such as CAN, EPG can provide signal patterns for testing and running diagnostic inside the C2000™ device.
For more information on the EPG module on a specific C2000 device, see the device-specific data sheet and the corresponding Technical Reference Manual (TRM).
This application report was written using the TMS320F28003x family of devices. The data sheet and TRM used for this application report are listed below:
Additional support is provided by the TI E2E™ Community.
The EPG can be used to generate clock signals. These clock signals can be used internally by the EPG (the EPG SIGGENx modules), or be exported out of the EPG through EPGOUTx signals. If exported out of the EPG through the EPGOUTx signals, then these clock signals can be used by other peripherals through the XBARs (EPGOUTs are connected to Output XBAR and CLB Output XBAR for F28003x) or be sent out of the device through GPIOs.
For example, for F28003x, EPG1 EPGOUT0 and EPGOUT1 are connected to Output XBAR. Therefore, EPGOUT0 and EPGOUT1 can be sent out of the device through GPIOs configured for Output XBAR. Also, on F28003x, the EPG1 EPGOUT2 and EPGOUT3 are connected to CLB Output XBAR, therefore; they can also be sent out of the device through GPIOs.
The EPG CLKGEN modules generate two version of output signals. The DCLK outputs are approximately 50% duty while the GCLK are the gated clocks. DCLKs can be exported out of the EPG module through EPGOUTx signals. GCLKs are used by the SIGGEN modules inside the EPG.