This application note describes the operation of the dual clock comparator (DCC) computation tool, made to be used with the Sitara™ AM263x MCU. This tool provides the pre-computed register values to be programmed, in order to check if any required system/peripheral clock frequency is within a specific accuracy % by comparing it against a reference clock, enabling easy integration into your application code.
The spreadsheet mentioned in this document can be downloaded from the following URL: https://www.ti.com/lit/zip/sprad69.
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Dual clock comparator (DCC) is primarily intended to determine the clock accuracy during the application execution. The exact accuracy is programmable and should be calculated for each application. It can also be used to determine the frequency of any selectable clock, using another independent input clock as a reference. It uses two independent clock sources to detect when one is out of spec.
Clock frequency drift is inevitable, which can occur due to multiple reasons such as environmental conditions like humidity, pressure and temperature, aging, and so forth. Impact of aging can be noticed when the device has been on the field for a few years, and the clocks start drifting causing catastrophic implications if not monitored. Hence, DCC is particularly useful in safety critical automotive/ industrial timing applications.
DCC contains three counters – counter0 (20-bit), valid0 (16-bit) and counter1 (20-bit). Initially, all counters are loaded with their user-defined, pre-load value. Counter0 and counter1 start decrementing once the DCC is enabled at rates determined by the frequencies of clock0 and clock1, respectively. When counter0 equals 0 (expires), the valid0 counter decrements at a rate determined by clock0. If counter1 decrements to 0 in the valid window, then no error is generated and clock1 is considered to be good within allowable tolerance as configured by the user. An error is generated when the frequency is not within the allowable tolerance, and counter1 doesn't decrement within the valid window (either when clock0 /clock1 is absent or clock1 expired before the counter0 reaches 0 or clock1 expired after both counter0 and valid0 reach 0).
Counter0 and counter1 are configured based on the ratio between the frequencies of clock0 and clock1 (Fclk1×Counter0 = Fclk0×Counter1). The valid0 counter provides tolerance and is configured based on the allowed frequency error and the inherent DCC error (asynchronous and digitization error). Since clock0 and clock1 are asynchronous, the start and stop of the counters do not occur synchronously. Hence, while configuring the counters, two different sources of errors must be accounted for, which are:
The following formulas are used by the tool to compute the counter0, valid0 and counter1 seed values:
Where,
The DCC computation tool provides the register values to be programmed in-order to compare any given system or peripheral clock against a configurable reference clock to determine if the frequency of the said clock is within the expected accuracy. The accuracy required can be provided as an input, and the tool calculates the counter seed values based on that. There is a separate calculator present for each of the four instances: DCC0, DCC1, DCC2 and DCC3.
Identify the DCC instance that can be used to monitor the clock source that you require, from the tool or the device technical reference manual.
At the end of the DCC completion phase, the DCC generates a DCC_done interrupt to R5F if the clock is within the configured tolerance. The Done bit (bit 1) in the register DCCSTAT(@0x00000014) will be set to 1 to indicate the completion.
If the DCC detects an error in the frequency measurement, then it generates DCCx_error to ESM (Error signaling module) instead of the DCC_done interrupt to R5F. The Error status (bit 0) in the register DCCSTAT(@0x00000014) will be set to 1 to indicate Error condition. In this case, the ESM can be configured to generate an interrupt to R5F or Device Error pin for further action. See the device technical reference manual for details on configuring and setting up the interrupts.
If interrupt mode is not used, after configuring the SINGLE_SHOT mode, R5F can be configured to continuously poll Error status (bit 0) and Done bit (bit 1) in the register DCCSTAT(@0x00000014).
The above example is for DCC0. Follow similar procedure to use any of the other DCC instances DCC1, DCC2 and DCC3.