SPRZ439H January 2017 – February 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
This document describes the known exceptions to the functional specifications (advisories). This document may also contain usage notes. Usage notes describe situations where the device's behavior may not match presumed or documented behavior. This may include behaviors that affect device performance or functional correctness.
NUMBER | TITLE | SILICON REVISIONS AFFECTED | ||
---|---|---|---|---|
0 | A | B | ||
Section 3.1.1 | PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear | Yes | Yes | Yes |
Section 3.1.2 | FPU32 and VCU Back-to-Back Memory Accesses | Yes | Yes | Yes |
Section 3.1.3 | Caution While Using Nested Interrupts | Yes | Yes | Yes |
Section 3.1.4 | Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature | Yes | Yes | Yes |