SNAS598B July   2012  – July 2015 LM4549B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  ADC Inputs and Outputs
      2. 8.3.2  Analog Mixing: MIX1
      3. 8.3.3  DAC Mixing and 3D Processing
      4. 8.3.4  Analog Mixing: MIX2
      5. 8.3.5  Stereo Mix
      6. 8.3.6  Stereo Outputs
      7. 8.3.7  Mono Output
      8. 8.3.8  Analog Loopthrough and Digital Loopback
      9. 8.3.9  Resets
      10. 8.3.10 Backwards Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Modes
      2. 8.4.2 Test Modes
    5. 8.5 Programming
      1. 8.5.1 AC Link Serial Interface Protocol
        1. 8.5.1.1 AC Link Output Frame: SDATA_OUT, Controller Output to LM4549B Input
          1. 8.5.1.1.1 SDATA_OUT: Slot 0 - Tag Phase
          2. 8.5.1.1.2 SDATA_OUT: Slot 1 - Read/Write, Control Address
          3. 8.5.1.1.3 SDATA_OUT: Slot 2 - Control Data
          4. 8.5.1.1.4 SDATA_OUT: Slots 3 & 4 - PCM Playback Left/Right Channels
          5. 8.5.1.1.5 SDATA_OUT: Slots 5 to 12 - Reserved
        2. 8.5.1.2 AC Link Input Frame: SDATA_IN, Controller Input from LM4549B Output
          1. 8.5.1.2.1 SDATA_IN: Slot 0 - Codec/Slot Status Bits
          2. 8.5.1.2.2 SDATA_IN: Slot 1 - Status Address / Slot Request Bits
          3. 8.5.1.2.3 SDATA_IN: Slot 2 - Status Data
          4. 8.5.1.2.4 SDATA_IN: Slot 3 - PCM Record Left Channel
          5. 8.5.1.2.5 SDATA_IN: Slot 4 - PCM Record Right Channel
          6. 8.5.1.2.6 SDATA_IN: Slots 5 to 12 - Reserved
      2. 8.5.2 Multiple Codecs
        1. 8.5.2.1 Extended AC Link
        2. 8.5.2.2 Secondary Codec Register Access
          1. 8.5.2.2.1 Slot 0: TAG bits in Output Frames (Controller to Codec)
          2. 8.5.2.2.2 Extended Audio ID register (28h): Support for Multiple Codecs
    6. 8.6 Register Maps
      1. 8.6.1  Reset Register (00h)
      2. 8.6.2  Master Volume Register (02h)
      3. 8.6.3  Line Level Volume Register (04h)
      4. 8.6.4  Mono Volume Register (06h)
      5. 8.6.5  PC Beep Volume Register (0Ah)
      6. 8.6.6  Mixer Input Volume Registers (Index 0Ch - 18h)
      7. 8.6.7  Record Select Register (1Ah)
      8. 8.6.8  Record Gain Register (1Ch)
      9. 8.6.9  General Purpose Register (20h)
      10. 8.6.10 3D Control Register (22h)
      11. 8.6.11 Power-Down Control / Status Register (26h)
      12. 8.6.12 Extended Audio ID Register (28h)
      13. 8.6.13 Extended Audio Status/Control register (2Ah)
      14. 8.6.14 Sample Rate Control Registers (2Ch, 32h)
      15. 8.6.15 Vendor ID Registers (7Ch, 7Eh)
      16. 8.6.16 Reserved Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 System Example
      1. 9.3.1 Improving System Performance
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Compliant With AC '97 Rev 2.1
  • High-Quality Sample Rate Conversion from 4 kHz to 48 kHz in 1-Hz Increments
  • Multiple Codec Support
  • True Line Level Output with Separate Gain Control
  • Texas Instrument's 3D Sound Stereo Enhancement Circuitry
  • Advanced Power Management Support
  • External Amplifier Power Down (EAPD) Control
  • PC-Beep Passthrough to Line Out During Initialization or Cold Reset
  • Digital 3.3-V and 5-V Supply Options
  • Extended Temperature: −40°C ≤ TA ≤ 85°C
  • Key Specifications
    • Analog Mixer Dynamic Range: 97 dB (Typical)
    • DAC Dynamic Range: 89 dB (Typical)
    • ADC Dynamic Range: 90 dB (Typical)

2 Applications

  • Desktop PC Audio Systems on PCI Cards, AMR Cards, or With Motherboard Chips Sets Featuring AC Link
  • Portable PC Systems as on MDC Cards, or With a Chipset or Accelerator Featuring AC Link
  • General and Multichannel Audio Frequency Systems
  • Automotive Telematics

3 Description

The LM4549B device is an audio codec for PC systems which is fully compliant with the PC99 and performs the analog intensive functions of the AC '97 Rev 2.1 architecture. Using 18-bit sigma-delta ADCs and DACs, the LM4549B provides 90 dB of dynamic range.

The LM4549B was designed specifically to provide a high quality audio path and provide all analog functionality in a PC audio system. It features full duplex stereo ADCs and DACs and analog mixers with access to 4 stereo and 4 mono inputs. Each mixer input has separate gain, attenuation and mute control and the mixers drive 1 mono- and 2-stereo outputs, each with attenuation and mute control. The LM4549B supports Texas Instrument's 3D Sound stereo enhancement and a comprehensive sample rate conversion capability. The sample rate for the ADCs and DACs can be programmed separately with a resolution of 1 Hz to convert any rate in the range 4 kHz – 48 kHz. Sample timing from the ADCs and sample request timing for the DACs are completely deterministic to ease task scheduling and application software development. These features together with an extended temperature range also make the LM4549B suitable for non-PC codec applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM4549B LQFP (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

LM4549B 20123501.gif