SNAS425C October   2007  – October 2014 LM98519

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Serial Interface Timing
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Input Clamping and Biasing Circuitry
      2. 7.3.2 Input Connections for 3 Channel Operation
      3. 7.3.3 AFE References
      4. 7.3.4 Offset Control
      5. 7.3.5 Black Level Calibration (Offset)
        1. 7.3.5.1 Manual Offset Adjustment
        2. 7.3.5.2 Automatic Offset Adjustment
        3. 7.3.5.3 Gain Control
        4. 7.3.5.4 White Level Calibration (AGC - Automatic Gain Control)
      6. 7.3.6 Operating Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 AFEPHASEn Details for SHP/SHD Input Mode
      2. 7.4.2 AFEPHASEn Details for SAMPLE and HOLD Input Mode
      3. 7.4.3 AFEPHASEn: 6 Channel and 3 Channel Modes
      4. 7.4.4 LM98519 AFEPHASE Synchronization
      5. 7.4.5 Sampling Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1  Using Black Pixel Average
      2. 7.5.2  Sample Timing Control
      3. 7.5.3  Timing Monitor Outputs
      4. 7.5.4  Output Data Test Pattern Generation
      5. 7.5.5  Fixed Pattern
      6. 7.5.6  Horizontal Gradation
      7. 7.5.7  Vertical Gradation
      8. 7.5.8  Lattice Pattern
      9. 7.5.9  Serial Interface
      10. 7.5.10 Serial Write
      11. 7.5.11 Serial Read
    6. 7.6 Register Maps
      1. 7.6.1 Configuration Registers
      2. 7.6.2 Configuration Register Details
  8. 8 Application and Implementation
    1. 8.1 Design Requirements
    2. 8.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 Over Voltage Protection on OS Inputs
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • 3.3-V Single Supply Operation
  • CDS or S/H Processing with Negative Input Signal Polarity
  • 32.5-MHz Channel Rate
  • Enhanced ESD Protection on Host Interface Pins: SHP, SHD, CLPIN, BLKCLP, AGC_ONB, MCLK, RESETB, SENB, SCLK, SDI, SDO
  • Low Power CMOS Design
  • 4-Wire Serial interface
  • 2 Channel Symmetrical Architecture
  • Independent Gain and Offset Correction for Each Channel
  • Digital Black Level Calibration for Each Channel
  • Digital White Level Calibration for Each Channel
  • Programmable Input Clamp

2 Applications

  • Digital Color Copiers
  • Scanners
  • Image Processing Polarity applications
  • Key Specifications
    • Maximum Input Level:
      • 1.19 Vp-p (CDS Gain = 1.0)
      • 0.58 Vp-p (CDS Gain = 2.1)
    • Input Sample Rate:
      • 5 to 32.5 MSPS – 6ch Mode
      • 10 to 32.5 MSPS – 3ch Mode
    • PGA Gain Range: 1x to 10x (0 to 20 dB)
    • CDS/SH Gain Settings: 1x or 2.1x
    • Total Channel Gain: 1x to 20x (0 to 26 dB)
    • PGA Gain Resolution: 8 Bits – Analog
    • ADC Resolution: 10 Bits
    • ADC Sampling Rate: 10 to 65 MSPS
    • SNR: 67.5 dB (Gain = 1x)
    • Offset DAC Range:
      • ±111 mV or ±60 mV – FDAC
      • ±277 mV – CDAC
    • Offset DAC Resolution:
      • ±10 Bits – FDAC
      • ±4 Bits – CDAC
    • Supply Voltage: 3.0 V to 3.6 V
    • Power Dissipation: 1.04 W (Typical)

3 Description

The LM98519 is a fully integrated, high performance 10-Bit, 65 MSPS signal processing solution for digital color copiers, scanners, and other image processing applications. High-speed signal throughput is achieved with an innovative six channel architecture utilizing Correlated Double Sampling (CDS), or Sample and Hold (SH) type sampling. 1x or 2x gain settings are available in the CDS/SH input stage. Each channel has a dedicated 1x to 10x (8 bit) PGA that allows accurate gain adjustment of each channel. The Digital White Level auto calibration loop can automatically set the PGA value to achieve a selected white target level. Each channel also has a ±4-bit coarse and ±10-bit fine analog offset correction DAC that allows offset correction before the sample-and-hold amplifier. These correction values can be controlled by an automated Digital Black Level correction loop. The PGA and offset DACs for each channel are programmed independently allowing unique values of gain and offset for each of the six channels. A 2-to-1 multiplexing scheme routes the signals to three 65-MHz high performance ADCs. The fully differential processing channels achieve exceptional noise immunity, having a very low noise floor of -67.5 dB. The 10-bit analog-to-digital converters have excellent dynamic performance making the LM98519 transparent in the image reproduction chain.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM98519 TQFP (80) 12.00 mm × 12.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

channel_block_diagram.gif

4 Revision History

Changes from B Revision (April 2013) to C Revision

  • Added, updated, or revised the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering InformationGo
  • Changed 68 db to 67.5 db in Description section.Go

Changes from A Revision (April 2013) to B Revision

  • Changed layout of National data sheet to TI formatGo