SLAS639L July   2011  – December 2017 MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram - RHA Package - MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739
    2. 4.2 Pin Diagram - DA Package - MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739
    3. 4.3 Pin Diagram - RGE Package - MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738
    4. 4.4 Pin Diagram - YQD Package - MSP430FR5738
    5. 4.5 Pin Diagram - PW Package - MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738
    6. 4.6 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    8. 5.8  Inputs - Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    10. 5.10 Outputs - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    11. 5.11 Output Frequency - General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    12. 5.12 Typical Characteristics - Outputs
    13. 5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode
    14. 5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode
    15. 5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    16. 5.16 DCO Frequencies
    17. 5.17 MODOSC
    18. 5.18 PMM, Core Voltage
    19. 5.19 PMM, SVS, BOR
    20. 5.20 Wake-up Times From Low-Power Modes
    21. 5.21 Timer_A
    22. 5.22 Timer_B
    23. 5.23 eUSCI (UART Mode) Clock Frequency
    24. 5.24 eUSCI (UART Mode)
    25. 5.25 eUSCI (SPI Master Mode) Clock Frequency
    26. 5.26 eUSCI (SPI Master Mode)
    27. 5.27 eUSCI (SPI Slave Mode)
    28. 5.28 eUSCI (I2C Mode)
    29. 5.29 10-Bit ADC, Power Supply and Input Range Conditions
    30. 5.30 10-Bit ADC, Timing Parameters
    31. 5.31 10-Bit ADC, Linearity Parameters
    32. 5.32 REF, External Reference
    33. 5.33 REF, Built-In Reference
    34. 5.34 REF, Temperature Sensor and Built-In VMID
    35. 5.35 Comparator_D
    36. 5.36 FRAM
    37. 5.37 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Functional Block Diagrams
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM
    9. 6.9  Memory Protection Unit (MPU)
    10. 6.10 Peripherals
      1. 6.10.1  Digital I/O
      2. 6.10.2  Oscillator and Clock System (CS)
      3. 6.10.3  Power-Management Module (PMM)
      4. 6.10.4  Hardware Multiplier (MPY)
      5. 6.10.5  Real-Time Clock (RTC_B)
      6. 6.10.6  Watchdog Timer (WDT_A)
      7. 6.10.7  System Module (SYS)
      8. 6.10.8  DMA Controller
      9. 6.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.10.10 TA0, TA1
      11. 6.10.11 TB0, TB1, TB2
      12. 6.10.12 ADC10_B
      13. 6.10.13 Comparator_D
      14. 6.10.14 CRC16
      15. 6.10.15 Shared Reference (REF)
      16. 6.10.16 Embedded Emulation Module (EEM)
      17. 6.10.17 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P2 (P2.7) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P3 (P3.4 to P3.6) Input/Output With Schmitt Trigger
      10. 6.11.10 Port Port P3 (P3.7) Input/Output With Schmitt Trigger
      11. 6.11.11 Port Port P4 (P4.0) Input/Output With Schmitt Trigger
      12. 6.11.12 Port Port P4 (P4.1) Input/Output With Schmitt Trigger
      13. 6.11.13 Port Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      14. 6.11.14 Port Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
  7. 7Device and Documentation Support
    1. 7.1  Getting Started
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Device Overview

1.1 Features

  • Embedded Microcontroller
    • 16-Bit RISC Architecture up to 24-MHz Clock
    • Wide Supply Voltage Range (2 V to 3.6 V)
    • –40°C to 85°C Operation
  • Optimized Ultra-Low-Power Modes
    • Active Mode: 81.4 µA/MHz (Typical)
    • Standby (LPM3 With VLO): 6.3 µA (Typical)
    • Real-Time Clock (RTC) (LPM3.5 With Crystal): 1.5 µA (Typical)
    • Shutdown (LPM4.5): 0.32 µA (Typical)
  • Ultra-Low-Power Ferroelectric RAM (FRAM)
    • Up to 16KB of Nonvolatile Memory
    • Ultra-Low-Power Writes
    • Fast Write at 125 ns per Word (16KB in 1 ms)
    • Built-In Error Correction Coding (ECC) and Memory Protection Unit (MPU)
    • Universal Memory = Program + Data + Storage
    • 1015 Write Cycle Endurance
    • Radiation Resistant and Nonmagnetic
  • Intelligent Digital Peripherals
    • 32-Bit Hardware Multiplier (MPY)
    • Three-Channel Internal DMA
    • Real-Time Clock (RTC) With Calendar and Alarm Functions
    • Five 16-Bit Timers With up to Three Capture/Compare Registers
    • 16-Bit Cyclic Redundancy Checker (CRC)
  • High-Performance Analog
    • 16-Channel Analog Comparator With Voltage Reference and Programmable Hysteresis
    • 12-Channel 10-Bit Analog-to-Digital Converter (ADC) With Internal Reference and Sample-and-Hold
      • 200 ksps at 100-µA Consumption
  • Enhanced Serial Communication
    • eUSCI_A0 and eUSCI_A1 Support:
      • UART With Automatic Baud-Rate Detection
      • IrDA Encode and Decode
      • SPI
    • eUSCI_B0 Supports:
      • I2C With Multiple-Slave Addressing
      • SPI
    • Hardware UART Bootloader (BSL)
  • Power Management System
    • Fully Integrated LDO
    • Supply Voltage Supervisor for Core and Supply Voltages With Reset Capability
    • Always-On Zero-Power Brownout Detection
    • Serial Onboard Programming With No External Voltage Needed
  • Flexible Clock System
    • Fixed-Frequency DCO With Six Selectable Factory-Trimmed Frequencies (Device Dependent)
    • Low-Power Low-Frequency Internal Clock Source (VLO)
    • 32-kHz Crystals (LFXT)
    • High-Frequency Crystals (HFXT)
  • Development Tools and Software
  • Family Members

1.2 Applications

  • Home Automation
  • Security
  • Sensor Management
  • Data Acquisition

CAUTION These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such as those experienced during reflow or hand soldering. See Absolute Maximum Ratings for more information.
CAUTION System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturb of data or code memory. See MSP430™ System-Level ESD Considerations for more information.

1.3 Description

The TI MSP430FR573x family of ultra-low-power microcontrollers consists of multiple devices that feature embedded FRAM nonvolatile memory, ultra-low-power 16-bit MSP430™ CPU, and different peripherals targeted for various applications. The architecture, FRAM, and peripherals, combined with seven low-power modes, are optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and reliability of flash, all at lower total power consumption. Peripherals include a 10-bit ADC, a 16-channel comparator with voltage reference generation and hysteresis capabilities, three enhanced serial channels capable of I2C, SPI, or UART protocols, an internal DMA, a hardware multiplier, an RTC, five 16-bit timers, and digital I/Os.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE(2)
MSP430FR5739RHA VQFN (40) 6 mm × 6 mm
MSP430FR5739DA TSSOP (38) 12.5 mm × 6.2 mm
MSP430FR5738RGE VQFN (24) 4 mm × 4 mm
MSP430FR5738PW TSSOP (28) 9.7 mm × 4.4 mm
MSP430FR5738YQD DSBGA (24) 2 mm × 2 mm
(1) For the most current part, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.
(2) The dimensions shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram for the MSP430FR5731, MSP430FR5735, and MSP430FR5739 devices in the RHA package. For the functional block diagrams for all device variants and package options, see Section 6.1.

MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 slas639-blk_fr5739_35_31_rha.gif Figure 1-1 Functional Block Diagram – RHA Package – MSP430FR5731, MSP430FR5735, MSP430FR5739