SLOS836E May   2013  – June 2016 TAS5729MD

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Related Devices
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital I/O Pins
    6. 7.6  Master Clock
    7. 7.7  Serial Audio Port
    8. 7.8  Protection Circuitry
    9. 7.9  Speaker Amplifier in All Modes
    10. 7.10 Speaker Amplifier in Stereo Bridge Tied Load (BTL) Mode
    11. 7.11 Speaker Amplifier in Stereo Post-Filter Parallel Bridge Tied Load (Post-Filter PBTL) Mode
    12. 7.12 Headphone Amplifier and Line Driver
    13. 7.13 Reset Timing
    14. 7.14 I2C Control Port
    15. 7.15 Typical Electrical Power Consumption
    16. 7.16 Typical Characteristics
      1. 7.16.1 Speaker Amplifier
      2. 7.16.2 Headphone Amplifier
      3. 7.16.3 Line Driver
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Supply
      2. 9.3.2  ADR/SPK_FAULT
      3. 9.3.3  Device Protection System
        1. 9.3.3.1 Overcurrent (OC) Protection With Current Limiting
        2. 9.3.3.2 Overtemperature Protection
        3. 9.3.3.3 Undervoltage Error (UVE) and Power-On Reset (POR)
      4. 9.3.4  Clock, Auto Detection, and PLL
      5. 9.3.5  Serial Data Interface
      6. 9.3.6  PWM Section
      7. 9.3.7  I2C Compatible Serial Control Interface
      8. 9.3.8  Serial Interface Control And Timing
        1. 9.3.8.1 I2S Timing
        2. 9.3.8.2 Left-Justified
        3. 9.3.8.3 Right-Justified
      9. 9.3.9  Automatic Gain Limiting (AGL)
      10. 9.3.10 PWM Level Meter
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Protection Mode
      2. 9.4.2 Speaker Amplifier Mode
        1. 9.4.2.1 Stereo Mode
        2. 9.4.2.2 Monaural Mode
      3. 9.4.3 Headphone/Line Amplifier
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Control Interface
        1. 9.5.1.1 General I2C Operation
        2. 9.5.1.2 Single- and Multiple-Byte Transfers
        3. 9.5.1.3 Single-Byte Write
        4. 9.5.1.4 Multiple-Byte Write
        5. 9.5.1.5 Single-Byte Read
        6. 9.5.1.6 Multiple-Byte Read
      2. 9.5.2 26-Bit 3.23 Number Format
    6. 9.6 Register Maps
      1. 9.6.1  Clock Control Register (0x00)
      2. 9.6.2  Device ID Register (0x01)
      3. 9.6.3  Error Status Register (0x02)
      4. 9.6.4  System Control Register 1 (0x03)
      5. 9.6.5  Serial Data Interface Register (0x04)
      6. 9.6.6  System Control Register 2 (0x05)
      7. 9.6.7  Soft Mute Register (0x06)
      8. 9.6.8  Volume Registers (0x07, 0x08, 0x09)
      9. 9.6.9  Volume Configuration Register (0x0E)
      10. 9.6.10 Modulation Limit Register (0x10)
      11. 9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
      12. 9.6.12 PWM Shutdown Group Register (0x19)
      13. 9.6.13 Start/Stop Period Register (0x1A)
      14. 9.6.14 Oscillator Trim Register (0x1B)
      15. 9.6.15 BKND_ERR Register (0x1C)
      16. 9.6.16 Input Multiplexer Register (0x20)
      17. 9.6.17 Channel 4 Source Select Register (0x21)
      18. 9.6.18 PWM Output MUX Register (0x25)
      19. 9.6.19 AGL Control Register (0x46)
      20. 9.6.20 PWM Switching Rate Control Register (0x4F)
      21. 9.6.21 EQ Control (0x50)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Configuration With Headphone and Line Driver Amplifier
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Hardware Integration
          2. 10.2.1.2.2 Control and Software Integration
          3. 10.2.1.2.3 Recommended Start-Up and Shutdown Procedures
            1. 10.2.1.2.3.1 Initialization Sequence
            2. 10.2.1.2.3.2 Normal Operation
            3. 10.2.1.2.3.3 Shutdown Sequence
            4. 10.2.1.2.3.4 Power-Down Sequence
        3. 10.2.1.3 Application Curves for Stereo BTL Configuration with Headphone and Line Driver Amplifier
      2. 10.2.2 Mono PBTL Configuration with Headphone and Line Driver Amplifier
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 DVDD, AVDD, and DRVDD Supplies
    2. 11.2 PVDD Power Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Audio I/O Configuration:
    • Single Stereo I²S Input
    • Stereo BTL or Mono PBTL Operation
    • 8-kHz to 48-kHz Sample Rates
    • Headphone Amplifier and Line Driver
  • Audio Digital Signal Processing:
    • Digital Equalization
    • Two-Band Automatic Gain Limiting
    • Coarse and Fine Volume Control
    • PWM Level Meter
  • General Operational Features:
    • I²C Software Control With Programmable I²C Address (101010[R/W] or 101011[R/W])
    • AD, BD, Ternary Modulation
    • Overtemperature, Undervoltage, Clock, and Overcurrent Protection
  • Audio Performance (PVDD = 18 V, RLOAD = 8 Ω)
    • Idle Channel Noise = 56 µVrms
    • THD+N at 1 W, 1 kHz, = 0.15%
    • SNR = 105 dB (reference to 0 dBFS)

2 Applications

  • LCD/LED TV and Multipurpose Monitors
  • Sound Bars, Docking Stations, PC Audio
  • Consumer Audio Equipment

3 Description

The TAS5729MD is a stereo I²S input device which includes a digital auto processor with two-band automatic gain limiting (AGL), digital equalization, course and fine volume control, and PWM level meter. The AGL is an enhanced dynamic range compression (DRC) function. The device can operate from a wide PVDD power supply range to enable use in numerous applications. The TAS5729MD operates with a nominal supply voltage from 4.5 to 24 VDC. The device is controlled by an I²C control port. The device has an integrated DirectPath™ headphone amplifier and line driver to increase system-level integration and reduce total solution costs.

An optimal mix of thermal performance and device cost is provided in the 200-mΩ RDS(ON) of the output MOSFETs. Additionally, a thermally enhanced HTSSOP provides excellent operation in the elevated ambient temperatures found in today's modern consumer electronic devices.

The entire TAS5729xx family is pin-to-pin compatible allowing a single hardware solution to be used across several end application platforms. Additionally, the I²C register map in the entire TAS5729xx family is identical to ensure low development overhead to choose between devices based upon system level requirements.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TAS5729MD HTSSOP (48) 12.50 mm × 6.10 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Signal Processing Flow

TAS5729MD Process_Flow.gif

Power at 10% THD+N vs PVDD

TAS5729MD Plot 1.gif

NOTE:

Dashed lines represent thermally limited region.