SPRS737C August 2011 – April 2014 TMS320C5532 , TMS320C5533 , TMS320C5534 , TMS320C5535
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
These devices are members of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and are designed for low-power applications.
The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.
The general-purpose input and output functions, along with the 10-bit SAR ADC on the TMS320C5535, provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two secure digital (SD) peripherals, four Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface.
Additional peripherals include: a high-speed Universal Serial Bus (USB 2.0) device mode only (not available on TMS320C5532), a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.
In addition, the TMS320C5535 includes a tightly coupled FFT Hardware Accelerator. The tightly coupled FFT Hardware Accelerator supports 8- to 1024-point (in power of 2) real and complex-valued FFTs.
Furthermore, the device includes the following three integrated LDOs to power different sections of the device.
ANA_LDO (all devices) provides 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power-management circuits (VDDA_ANA).
DSP_LDO (TMS320C5535 and 'C5534) provides 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. For lowest power operation, the programmer can shut down the internal DSP_LDO, cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTC and DVDDRTC). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core. When DSP_LDO comes out of reset, it is enabled to 1.3 V for the bootloader to operate. For the 50-MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CVDD, for proper operation after reset.
USB_LDO (TMS320C5535, 'C5534, and 'C5533) provides 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).
These devices are supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The devices are also supported by the C55x DSP library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.
PART NUMBER | PACKAGE | BODY SIZE |
---|---|---|
TMS320C5535AZHH10 | BGA MICROSTAR (144) | 12.0 mm x 12.0 mm |
TMS320C5535AZHHA10 | BGA MICROSTAR (144) | 12.0 mm x 12.0 mm |
TMS320C5534AZHH10 | BGA MICROSTAR (144) | 12.0 mm x 12.0 mm |
TMS320C5534AZHHA10 | BGA MICROSTAR (144) | 12.0 mm x 12.0 mm |
Figure 1-1 shows the functional block diagram of the devices.
Changes from B Revision (February, 2012) to C Revision
Table 3-1 lists the important differences between the devices.
Device | Digital Core Supply Voltage (CVDD) | On-chip DARAM | On-chip SARAM | USB | LCD Interface | Tightly-Coupled FFT | SAR ADC | LDO | |
---|---|---|---|---|---|---|---|---|---|
1.05 V | 1.3 V | ||||||||
Maximum CPU Speed | |||||||||
TMS320C5535A05 | 50 MHz | - | 64KB | 256KB | √(1) | √ | √ | √ | ANA, DSP, and USB |
TMS320C5535A10 | 50 MHz | 100 MHz | |||||||
TMS320C5534A05 | 50 MHz | - | 64KB | 192KB | √ | -(2) | - | - | ANA, DSP, and USB |
TMS320C5534A10 | 50 MHz | 100 MHz | |||||||
TMS320C5533A05 | 50 MHz | - | 64KB | 64KB | √ | - | - | - | ANA and USB |
TMS320C5533A10 | 50 MHz | 100 MHz | |||||||
TMS320C5532A05 | 50 MHz | - | 64KB | 0KB | - | - | - | - | ANA only |
TMS320C5532A10 | 50 MHz | 100 MHz |
The following tables provide an overview of all the devices. The tables show significant features of each device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. For more detailed information on the actual device part number and maximum device operating frequency, see Section 7.1.2, Device Nomenclature.
HARDWARE FEATURES | TMS320C5535A05, C5535A10 | ||
---|---|---|---|
Peripherals Not all peripheral pins are available at the same time (for more detail, see Section 5). |
DMA | Four DMA controllers each with four channels, for a total of 16 channels |
|
Timers | 2 32-Bit General-Purpose (GP) Timers 1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog |
||
UART | 1 (with RTS and CTS flow control) | ||
SPI | 1 with 4 chip selects | ||
I2C | 1 (Master or Slave) | ||
I2S | 4 (Two Channel, Full Duplex Communication) | ||
USB 2.0 (Device only) | High- and Full-Speed Device | ||
SD | 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers | ||
LCD Bridge | 1 (8-bit or 16-bit asynchronous parallel bus) | ||
ADC (Successive Approximation [SAR]) | 1 (10-bit, 4 -input, 16-μs conversion time) | ||
Real-Time Clock (RTC) | 1 (Crystal Input, Separate Clock Domain and Power Supply) | ||
FFT Hardware Accelerator | 1 (Supports 8 to 1024-point 16-bit real and complex FFT) | ||
General-Purpose Input/Output Port (GPIO) | 32 pins (with 1 Additional General-Purpose Output (XF) and 4 Special-Purpose Outputs for Use With SAR Configure up to 20 pins simultaneously |
||
On-Chip Memory | Size (Bytes) | 320 KB RAM, 128KB ROM | |
Organization |
|
||
JTAG BSDL_ID | JTAGID Register (Value is: 0x1B8F E02F) |
see Figure 6-5 | |
CPU Frequency | MHz | 1.05-V Core | 50 MHz |
1.3-V Core | 100 MHz (TMS320C5535A10 only) | ||
Cycle Time | ns | 1.05-V Core | 20 ns |
1.3-V Core | 10 ns (TMS320C5535A10 only) | ||
Voltage | Core (V) | 1.05 V – 50 MHz | |
1.3 V – 100 MHz (TMS320C5535A10 only) | |||
I/O (V) | 1.8 V, 2.5 V, 2.75 V, 3.3 V | ||
LDOs | DSP_LDO | 1.3 V or 1.05 V, 250 mA max current for DSP CPU (CVDD) | |
ANA_LDO | 1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL), SAR, and power management circuits (VDDA_ANA) | ||
USB_LDO | 1.3 V, 25 mA max current to supply power to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3) | ||
Power Characterization | Active @ Room Temp 25°C, 75% DMAC + 25% ADD | 0.15 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz |
|
Active @ Room Temp 25°C, 75% DMAC + 25% NOP | 0.14 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) | 0.26 mW @ 1.05 V 0.44 mW @ 1.3 V |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) | 0.23 mW @ 1.05 V 0.40 mW @ 1.3 V |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) | 0.15 mW @ 1.05 V 0.28 mW @ 1.3 V |
||
PLL Options | Software Programmable Multiplier | x4 to x4099 multiplier | |
BGA Package | 12 x 12 mm | 144-Pin BGA (ZHH) | |
Product Status(1) | Product Preview (PP), Advance Information (AI), or Production Data (PD) |
PD |
HARDWARE FEATURES | TMS320C5534A05, C5534A10 | ||
---|---|---|---|
Peripherals Not all peripheral pins are available at the same time (for more detail, see Section 5). |
DMA | Four DMA controllers each with four channels, for a total of 16 channels | |
Timers | 2 32-Bit General-Purpose (GP) Timers 1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog |
||
UART | 1 (with RTS and CTS flow control) | ||
SPI | 1 with 4 chip selects | ||
I2C | 1 (Master or Slave) | ||
I2S | 4 (Two Channel, Full Duplex Communication) | ||
USB 2.0 (Device only) | High- and Full-Speed Device | ||
SD | 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers | ||
Real-Time Clock (RTC) | 1 (Crystal Input, Separate Clock Domain and Power Supply) | ||
General-Purpose Input/Output Port (GPIO) | Up to 20 pins (with 1 Additional General-Purpose Output (XF)) | ||
On-Chip Memory | Size (Bytes) | 256KB RAM, 128KB ROM | |
Organization |
|
||
JTAG BSDL_ID | JTAGID Register (Value is: 0x1B8F E02F) |
see Figure 6-5 | |
CPU Frequency | MHz | 1.05-V Core | 50 MHz |
1.3-V Core | 100 MHz (TMS320C5534A10 only) | ||
Cycle Time | ns | 1.05-V Core | 20 ns |
1.3-V Core | 10 ns (TMS320C5534A10 only) | ||
Voltage | Core (V) | 1.05 V – 50 MHz | |
1.3 V – 100 MHz (TMS320C5534A10 only) | |||
I/O (V) | 1.8 V, 2.5 V, 2.75 V, 3.3 V | ||
LDOs | DSP_LDO | 1.3 V or 1.05 V, 250 mA max current for DSP CPU (CVDD) | |
ANA_LDO | 1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL) and power management circuits (VDDA_ANA) | ||
USB_LDO | 1.3 V, 25 mA max current to supply power to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3) | ||
Power Characterization | Active @ Room Temp 25°C, 75% DMAC + 25% ADD | 0.15 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz |
|
Active @ Room Temp 25°C, 75% DMAC + 25% NOP | 0.14 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) | 0.26 mW @ 1.05 V 0.44 mW @ 1.3 V |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) | 0.23 mW @ 1.05 V 0.40 mW @ 1.3 V |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) | 0.15 mW @ 1.05 V 0.28 mW @ 1.3 V |
||
PLL Options | Software Programmable Multiplier | x4 to x4099 multiplier | |
BGA Package | 12 x 12 mm | 144-Pin BGA (ZHH) | |
Product Status(1) | Product Preview (PP), Advance Information (AI), or Production Data (PD) |
PD |
HARDWARE FEATURES | TMS320C5533A05, C5533A10 | ||
---|---|---|---|
Peripherals Not all peripheral pins are available at the same time (for more detail, see Section 5). |
DMA | Four DMA controllers each with four channels, for a total of 16 channels |
|
Timers | 2 32-Bit General-Purpose (GP) Timers 1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog |
||
UART | 1 (with RTS and CTS flow control) | ||
SPI | 1 with 4 chip selects | ||
I2C | 1 (Master or Slave) | ||
I2S | 4 (Two Channel, Full Duplex Communication) | ||
USB 2.0 (Device only) | High- and Full-Speed Device | ||
SD | 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers | ||
Real-Time Clock (RTC) | 1 (Crystal Input, Separate Clock Domain and Power Supply) | ||
General-Purpose Input/Output Port (GPIO) | Up to 20 pins (with 1 Additional General-Purpose Output (XF)) | ||
On-Chip Memory | Size (Bytes) | 128 KB RAM, 128KB ROM | |
Organization |
|
||
JTAG BSDL_ID | JTAGID Register (Value is: 0x1B8F E02F) |
see Figure 6-5 | |
CPU Frequency | MHz | 1.05-V Core | 50 MHz |
1.3-V Core | 100 MHz (TMS320C5533A10 only) | ||
Cycle Time | ns | 1.05-V Core | 20 ns |
1.3-V Core | 10 ns (TMS320C5533A10 only) | ||
Voltage | Core (V) | 1.05 V – 50 MHz | |
1.3 V – 100 MHz (TMS320C5533A10 only) | |||
I/O (V) | 1.8 V, 2.5 V, 2.75 V, 3.3 V | ||
LDOs | ANA_LDO | 1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL) and power management circuits (VDDA_ANA) | |
USB_LDO | 1.3 V, 25 mA max current to supply power to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3) | ||
Power Characterization | Active @ Room Temp 25°C, 75% DMAC + 25% ADD | 0.15 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz |
|
Active @ Room Temp 25°C, 75% DMAC + 25% NOP | 0.14 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) | 0.26 mW @ 1.05 V 0.44 mW @ 1.3 V |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) | 0.23 mW @ 1.05 V 0.40 mW @ 1.3 V |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) | 0.15 mW @ 1.05 V 0.28 mW @ 1.3 V |
||
PLL Options | Software Programmable Multiplier | x4 to x4099 multiplier | |
BGA Package | 12 x 12 mm | 144-Pin BGA (ZHH) | |
Product Status(1) | Product Preview (PP), Advance Information (AI), or Production Data (PD) |
PD |
HARDWARE FEATURES | TMS320C5532A05, C5532A10 | ||
---|---|---|---|
Peripherals Not all peripheral pins are available at the same time (for more detail, see Section 5). |
DMA | Four DMA controllers each with four channels, for a total of 16 channels |
|
Timers | 2 32-Bit General-Purpose (GP) Timers 1 Additional Timer Configurable as a 32-Bit GP Timer or a Watchdog |
||
UART | 1 (with RTS and CTS flow control) | ||
SPI | 1 with 4 chip selects | ||
I2C | 1 (Master or Slave) | ||
I2S | 4 (Two Channel, Full Duplex Communication) | ||
SD | 2 SD, 256-byte read and write buffer, max 50-MHz clock and signaling for DMA transfers | ||
Real-Time Clock (RTC) | 1 (Crystal Input, Separate Clock Domain and Power Supply) | ||
General-Purpose Input/Output Port (GPIO) | Up to 20 pins (with 1 Additional General-Purpose Output (XF)) | ||
On-Chip Memory | Size (Bytes) | 64KB RAM, 128KB ROM | |
Organization |
|
||
JTAG BSDL_ID | JTAGID Register (Value is: 0x1B8F E02F) |
see Figure 6-5 | |
CPU Frequency | MHz | 1.05-V Core | 50 MHz |
1.3-V Core | 100 MHz (TMS320C5532A10 only) | ||
Cycle Time | ns | 1.05-V Core | 20 ns |
1.3-V Core | 10 ns (TMS320C5532A10 only) | ||
Voltage | Core (V) | 1.05 V – 50 MHz | |
1.3 V – 100 MHz (TMS320C5532A10 only) | |||
I/O (V) | 1.8 V, 2.5 V, 2.75 V, 3.3 V | ||
LDO | ANA_LDO | 1.3 V, 4 mA max current for PLL (VDDA_PLL) power management circuits (VDDA_ANA) | |
Power Characterization | Active @ Room Temp 25°C, 75% DMAC + 25% ADD | 0.15 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz |
|
Active @ Room Temp 25°C, 75% DMAC + 25% NOP | 0.14 mW/MHz @ 1.05 V, 50 MHz 0.22 mW/MHz @ 1.3 V, 100 MHz |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM and SARAM in Active Mode) | 0.26 mW @ 1.05 V 0.44 mW @ 1.3 V |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Retention and SARAM in Active Mode) | 0.23 mW @ 1.05 V 0.40 mW @ 1.3 V |
||
Standby (Master Clock Disabled) @ Room Temp 25°C (DARAM in Active Mode and SARAM in Retention) | 0.15 mW @ 1.05 V 0.28 mW @ 1.3 V |
||
PLL Options | Software Programmable Multiplier | x4 to x4099 multiplier | |
BGA Package | 12 x 12 mm | 144-Pin BGA (ZHH) | |
Product Status(1) | Product Preview (PP), Advance Information (AI), or Production Data (PD) |
PD |