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The TPA3250 device is a high performance class-D power amplifier that enables true premium sound quality with class-D efficiency. It features an advanced integrated feedback design and proprietary high-speed gate driver error correction (PurePath™ Ultra-HD). This technology allows ultra low distortion across the audio band and superior audio quality. With a 32V power supply the device can drive up to 2 x 130 W peak into 4-Ω load and 2 x 70 W continuous into 8-Ω load and features a 2 VRMS analog input interface that works seamlessly with high performance DACs such as TI's PCM5242. In addition to excellent audio performance, TPA3250 achieves both high power efficiency and very low power stage idle losses below 1 W. This is achieved through the use of 60 mΩ MOSFETs and an optimized gate driver scheme that achieves significantly lower idle losses than typical discrete implementations.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPA3250 | HTSSOP (44) | 6.10mm x 14.00mm |
Changes from * Revision (December 2015) to A Revision
DEVICE NAME | DESCRIPTION |
TPA3251 | 175-W Stereo Class-D PurePath™ Ultra-HD Analog Input Audio Power Amplifier |
TPA3116D2 | 50W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance |
TPA3118D2 | 30W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance |
The TPA3250 is available in a thermally enhanced TSSOP package.
The package type contains a PowerPad™ that is located on the bottom side of the device for thermal connection to the PCB.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AVDD | 9 | P | Internal voltage regulator, analog section |
BST_A | 23 | P | HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required. |
BST_B | 24 | P | HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required. |
BST_C | 43 | P | HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required. |
BST_D | 44 | P | HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required. |
CLIP_OTW | 2 | O | Clipping warning and Over-temperature warning; open drain; active low |
C_START | 8 | O | Startup ramp, requires a charging capacitor to GND |
DVDD | 12 | P | Internal voltage regulator, digital section |
FAULT | 4 | O | Shutdown signal, open drain; active low |
FREQ_ADJ | 15 | O | Oscillator frequency programming pin |
GND | 10, 11, 25, 26, 33, 34, 41, 42 | P | Ground |
GVDD_AB | 22 | P | Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND |
GVDD_CD | 1 | P | Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND |
INPUT_A | 17 | I | Input signal for half bridge A |
INPUT_B | 18 | I | Input signal for half bridge B |
INPUT_C | 7 | I | Input signal for half bridge C |
INPUT_D | 6 | I | Input signal for half bridge D |
M1 | 20 | I | Mode selection 1 (LSB) |
M2 | 19 | I | Mode selection 2 (MSB) |
OC_ADJ | 16 | I/O | Over-Current threshold programming pin |
OSC_IOM | 14 | I/O | Oscillator synchronization interface |
OSC_IOP | 13 | O | Oscillator synchronization interface |
OUT_A | 27, 28 | O | Output, half bridge A |
OUT_B | 32 | O | Output, half bridge B |
OUT_C | 35 | O | Output, half bridge C |
OUT_D | 39, 40 | O | Output, half bridge D |
PVDD_AB | 29, 30, 31 | P | PVDD supply for half-bridge A and B |
PVDD_CD | 36, 37, 38 | P | PVDD supply for half-bridge C and D |
RESET | 5 | I | Device reset Input; active low |
VDD | 21 | P | Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling. |
VBG | 3 | P | Internal voltage reference requires a 0.1-µF capacitor to GND for decoupling. |
PowerPAD™ | P | Ground, connect to PCB copper pour. Placed on bottom side of device. |
MODE PINS | INPUT MODE | OUTPUT CONFIGURATION | DESCRIPTION | |||
---|---|---|---|---|---|---|
M2 | M1 | |||||
0 | 0 | 2N + 1 | 2 × BTL | Stereo BTL output configuration | ||
0 | 1 | 2N/1N + 1 | 1 x BTL + 2 x SE | 2.1 BTL + SE mode | ||
1 | 0 | 2N + 1 | 1 x PBTL | Parallelled BTL configuration. Connect INPUT_C and INPUT_D to GND. | ||
1 | 1 | 1N +1 | 4 x SE | Single ended output configuration |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | BST_X to GVDD_X(2) | –0.3 | 50 | V |
VDD to GND | –0.3 | 13.2 | V | |
GVDD_X to GND(2) | –0.3 | 13.2 | V | |
PVDD_X to GND(2) | –0.3 | 50 | V | |
DVDD to GND | –0.3 | 4.2 | V | |
AVDD to GND | –0.3 | 8.5 | V | |
VBG to GND | -0.3 | 4.2 | V | |
Interface pins | OUT_X to GND(2) | –0.3 | 50 | V |
BST_X to GND(2) | –0.3 | 62.5 | V | |
OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND | –0.3 | 4.2 | V | |
RESET, FAULT, CLIP_OTW, CLIP to GND | –0.3 | 4.2 | V | |
INPUT_X to GND | –0.3 | 7 | V | |
Continuous sink current, RESET, FAULT, CLIP_OTW, CLIP, RESET to GND | 9 | mA | ||
TJ | Operating junction temperature range | 0 | 150 | °C |
Tstg | Storage temperature range | –40 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
VESD | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | V |
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
PVDD_x | Half-bridge supply | DC supply voltage | 12 | 32 | 38 | V |
GVDD_x | Supply for logic regulators and gate-drive circuitry | DC supply voltage | 10.8 | 12 | 13.2 | V |
VDD | Digital regulator supply voltage | DC supply voltage | 10.8 | 12 | 13.2 | V |
RL(BTL) | Load impedance | Output filter inductance within recommended value range | 2.7 | 4 | Ω | |
RL(SE) | 1.5 | 3 | ||||
RL(PBTL) | 1.6 | 2 | ||||
LOUT(BTL) | Output filter inductance | Minimum output inductance at IOC | 5 | μH | ||
LOUT(SE) | 5 | |||||
LOUT(PBTL) | 5 | |||||
FPWM | PWM frame rate selectable for AM interference avoidance; 1% Resistor tolerance | Nominal | 430 | 450 | 470 | kHz |
AM1 | 475 | 500 | 525 | |||
AM2 | 575 | 600 | 625 | |||
R(FREQ_ADJ) | PWM frame rate programming resistor | Nominal; Master mode | 29.7 | 30 | 30.3 | kΩ |
AM1; Master mode | 19.8 | 20 | 20.2 | |||
AM2; Master mode | 9.9 | 10 | 10.1 | |||
CPVDD | PVDD close decoupling capacitors | 1.0 | μF | |||
ROC | Over-current programming resistor | Resistor tolerance = 5% | 22 | 30 | kΩ | |
ROC(LATCHED) | Over-current programming resistor | Resistor tolerance = 5% | 47 | 64 | kΩ | |
V(FREQ_ADJ) | Voltage on FREQ_ADJ pin for slave mode operation | Slave mode | 3.3 | V | ||
TJ | Junction temperature | 0 | 125 | °C |
THERMAL METRIC(1) | TPA3250 | UNIT | ||
---|---|---|---|---|
DDV 44-PINS HTSSOP | ||||
JEDEC STANDARD 4 LAYER PCB | ||||
RθJA | Junction-to-ambient thermal resistance | 26.0 | °C/W | |
RθJC(top) | Junction-to-case (top) thermal resistance | 10.2 | °C/W | |
RθJB | Junction-to-board thermal resistance | 6.5 | °C/W | |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W | |
ψJB | Junction-to-board characterization parameter | 6.5 | °C/W | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION | ||||||
DVDD | Voltage regulator, only used as reference node | VDD = 12 V | 3 | 3.3 | 3.6 | V |
AVDD | Voltage regulator, only used as reference node | VDD = 12 V | 7.8 | V | ||
IVDD | VDD supply current | Operating, 50% duty cycle | 40 | mA | ||
Idle, reset mode | 13 | |||||
IGVDD_X | Gate-supply current per full-bridge | 50% duty cycle | 25 | mA | ||
Reset mode | 3 | |||||
IPVDD_X | PVDD idle current per full bridge | 50% duty cycle with 10µH Output Filter Inductors | 12.5 | mA | ||
Reset mode, No switching | 1 | mA | ||||
ANALOG INPUTS | ||||||
RIN | Input resistance | 24 | kΩ | |||
VIN | Maximum input voltage swing | 7 | V | |||
IIN | Maximum input current | 1 | mA | |||
G | Inverting voltage Gain | VOUT/VIN | 20 | dB | ||
OSCILLATOR | ||||||
fOSC(IO+) | Nominal, Master Mode | FPWM × 6 | 2.58 | 2.7 | 2.82 | MHz |
AM1, Master Mode | 2.85 | 3 | 3.15 | |||
AM2, Master Mode | 3.45 | 3.6 | 3.75 | |||
VIH | High level input voltage | 1.86 | V | |||
VIL | Low level input voltage | 1.45 | V | |||
OUTPUT-STAGE MOSFETs | ||||||
RDS(on) | Drain-to-source resistance, low side (LS) | TJ = 25°C, Includes metallization resistance, GVDD = 12 V |
60 | 100 | mΩ | |
Drain-to-source resistance, high side (HS) | 60 | 100 | mΩ | |||
I/O PROTECTION | ||||||
Vuvp,VDD,GVDD | Undervoltage protection limit, GVDD_x and VDD | 9.5 | V | |||
Vuvp,VDD, GVDD,hyst (1) | 0.6 | V | ||||
OTW | Overtemperature warning, CLIP_OTW(1) | 115 | 125 | 135 | °C | |
OTWhyst (1) | Temperature drop needed below OTW temperature for CLIP_OTW to be inactive after OTW event. | 25 | °C | |||
OTE(1) | Overtemperature error | 145 | 155 | 165 | °C | |
OTE-OTW(differential) (1) | OTE-OTW differential | 30 | °C | |||
OTEhyst (1) | A reset needs to occur for FAULT to be released following an OTE event | 25 | °C | |||
OLPC | Overload protection counter | fPWM = 450 kHz | 2.3 | ms | ||
IOC | Overcurrent limit protection | Resistor – programmable, nominal peak current in 1Ω load, ROCP = 22 kΩ | 14 | A | ||
IOC(LATCHED) | Overcurrent limit protection | Resistor – programmable, peak current in 1Ω load, ROCP = 47kΩ | 14 | A | ||
IDCspkr | DC Speaker Protection Current Threshold | BTL current imbalance threshold | 1.5 | A | ||
IOCT | Overcurrent response time | Time from switching transition to flip-state induced by overcurrent. | 150 | ns | ||
IPD | Output pulldown current of each half | Connected when RESET is active to provide bootstrap charge. Not used in SE mode. | 3 | mA | ||
STATIC DIGITAL SPECIFICATIONS | ||||||
VIH | High level input voltage | M1, M2, OSC_IOP, OSC_IOM, RESET | 1.9 | V | ||
VIL | Low level input voltage | 0.8 | V | |||
Ilkg | Input leakage current | 100 | μA | |||
OTW/SHUTDOWN (FAULT) | ||||||
RINT_PU | Internal pullup resistance, CLIP_OTW to DVDD, FAULT to DVDD | 20 | 26 | 32 | kΩ | |
VOH | High level output voltage | Internal pullup resistor | 3 | 3.3 | 3.6 | V |
VOL | Low level output voltage | IO = 4 mA | 200 | 500 | mV | |
Device fanout | CLIP_OTW, FAULT | No external pullup | 30 | devices |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PO | Power output per channel | RL = 8 Ω, 10% THD+N | 70 | W | ||
RL = 4 Ω, 10% THD+N, 3 seconds Peak Power(1) | 130 | |||||
RL = 4 Ω, 10% THD+N, Single Channel, 300 seconds duration(1) | 130 | |||||
RL = 8 Ω, 1% THD+N | 60 | |||||
RL = 4 Ω, 1% THD+N | 40 | |||||
RL = 4 Ω, 1% THD+N, 6 seconds Peak Power(1) | 105 | |||||
RL = 4 Ω, 1% THD+N, Single Channe(1)l | 105 | |||||
THD+N | Total harmonic distortion + noise | 1 W | 0.005% | |||
Vn | Output integrated noise | A-weighted, AES17 filter, Input Capacitor Grounded | 60 | μV | ||
|VOS| | Output offset voltage | Inputs AC coupled to GND | 20 | 60 | mV | |
SNR | Signal-to-noise ratio(2) | 112 | dB | |||
DNR | Dynamic range | 112 | dB | |||
Pidle | Power dissipation due to Idle losses (IPVDD_X) | PO = 0, 4 channels switching(3) | 0.6 | W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PO | Power output per channel | RL = 4 Ω, 10% THD+N | 33 | W | ||
RL = 3 Ω, 10% THD+N | 42 | |||||
RL = 4 Ω, 1% THD+N | 27 | |||||
RL = 3 Ω, 1% THD+N | 34 | |||||
THD+N | Total harmonic distortion + noise | 1 W | 0.015% | |||
Vn | Output integrated noise | A-weighted, AES17 filter, Input Capacitor Grounded | 111 | μV | ||
SNR | Signal to noise ratio(1) | A-weighted | 100 | dB | ||
DNR | Dynamic range | A-weighted | 100 | dB | ||
Pidle | Power dissipation due to idle losses (IPVDD_X) | PO = 0, 4 channels switching(2) | 0.5 | W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PO | Power output per channel | RL = 8 Ω, 10% THD+N | 75 | W | ||
RL = 4 Ω, 10% THD+N | 145 | |||||
RL = 3 Ω, 10% THD+N | 189 | |||||
RL = 8 Ω, 1% THD+N | 60 | |||||
RL = 4 Ω, 1% THD+N | 115 | |||||
RL = 3 Ω, 1% THD+N | 150 | |||||
THD+N | Total harmonic distortion + noise | 1 W | 0.015% | |||
Vn | Output integrated noise | A-weighted, AES17 filter, Input Capacitor Grounded | 62 | μV | ||
SNR | Signal to noise ratio(1) | A-weighted | 112 | dB | ||
DNR | Dynamic range | A-weighted | 107 | dB | ||
Pidle | Power dissipation due to idle losses (IPVDD_X) | PO = 0, 4 channels switching(2) | 0.6 | W |
RL = 8 Ω | P = 1W, 10W, 40W | TA = 25°C |
RL = 8 Ω | TA = 25°C |
RL = 4 Ω, 8 Ω | THD+N = 1% | TA = 25°C |
RL = 4 Ω, 8 Ω | THD+N = 10% | TA = 25°C |
RL = 8 Ω | P = 1W, 10W, 40W | TA = 25°C |
AUX-0025 filter, 80 kHz analyzer BW |
RL = 4 Ω, 8 Ω | THD+N = 10% | TA = 25°C |
RL = 4 Ω, 8 Ω | THD+N = 10% | TA = 25°C |
8 Ω, VREF = 25.46 V (1% Output power) | FFT = 16384 | |||
AUX-0025 filter, 80 kHz analyzer BW | TA = 25°C |
RL = 3Ω, 4Ω | TA = 25°C |
RL = 4Ω | P = 1W, 10W, 25W | TA = 25°C |
AUX-0025 filter, 80 kHz analyzer BW |
RL = 3Ω, 4Ω | THD+N = 1% | TA = 25°C |
RL = 4Ω | P = 1W, 10W, 25W | TA = 25°C |
RL = 3Ω, 4Ω | THD+N = 10% | TA = 25°C |
RL = 4Ω, 8Ω | TA = 25°C |
RL = 4Ω | P = 1W, 20W, 75W | TA = 25°C |
AUX-0025 filter, 80 kHz analyzer BW |
RL = 3Ω, 4Ω | THD+N = 1% | TA = 25°C |
RL = 4Ω | P = 1W, 20W, 75W | TA = 25°C |
RL = 3Ω, 4Ω | THD+N = 10% | TA = 25°C |
All parameters are measured according to the conditions described in the Recommended Operating Conditions, Typical Characteristics, BTL Configuration, Typical Characteristics, SE Configuration and Typical Characteristics, PBTL Configuration sections.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can be used to reduce the out of band noise remaining on the amplifier outputs.
To facilitate system design, the TPA3250 needs only a 12-V supply in addition to the (typical) 32-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry, AVDD and DVDD. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
The audio signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_X). Power-stage supply pins (PVDD_X) and gate drive supply pins (GVDD_X) are separate for each full bridge. Although supplied from the same 12-V source, separating to GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details) is recommended. These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must be kept as short as possible and with as little area as possible to minimize induction (see reference board documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is decoupled with 1-μF ceramic capacitor placed as close as possible to the supply pins. It is recommended to follow the PCB layout of the TPA3250 reference design. For additional information on recommended power supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36-V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power supply is settled for minimum turn on audible artefacts. Moreover, the TPA3250 is fully protected against erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. The function is for protection-mode signaling to a system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when the device junction temperature exceeds 125°C (see Table 2).
FAULT | CLIP_OTW | DESCRIPTION |
---|---|---|
0 | 0 | Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction temperature higher than 125°C (overtemperature warning) |
0 | 0 | Overload (OLP) or undervoltage (UVP). Junction temperature higher than 125°C (overtemperature warning) |
0 | 1 | Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C |
1 | 0 | Junction temperature higher than 125°C (overtemperature warning) |
1 | 1 | Junction temperature lower than 125°C and no OLP or UVP faults (normal operation) |
Note that asserting either RESET low forces the FAULT signal high, independent of faults being present. TI recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an overtemperature warning signal by, that is, turning down the volume to prevent further heating of the device resulting in device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and CLIP_OTW outputs.
The TPA3250 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TPA3250 responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been removed, that is, the supply voltage has increased.
The device will function on errors, as shown in Table 3.
BTL | MODE | PBTL | MODE | SE | MODE |
---|---|---|---|---|---|
LOCAL ERROR IN | TURNS OFF | LOCAL ERROR IN | TURNS OFF | LOCAL ERROR IN | TURNS OFF |
A | A+B | A | A+B+C+D | A | A+B |
B | B | B | |||
C | C+D | C | C | C+D | |
D | D | D |
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching, does not assert FAULT).
TPA3250 has fast reacting current sensors with a programmable trip threshold (OC threshold) on all high-side and low-side FETs. To prevent output current to increase beyond the programmed threshold, TPA3250 has the option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control, CB3C) or to perform an immediate shutdown of the output in case of excess output current (Latching Shutdown). CB3C prevents premature shutdown due to high output current transients caused by high level music transients and a drop of real speaker’s load impedance, and allows the output current to be limited to a maximum programmed level. If the maximum output current persists, i.e. the power stage being overloaded with too low load impedance, the device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z) state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an over current event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning of next PWM frame.
During CB3C an over load counter increments for each over current event and decrease for each non-over current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown protection action. In the event of a short circuit condition, the over current protection limits the output current by the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum value. If a latched OC operation is required such that the device shuts down the affected output immediately upon first detected over current event, this protection mode should be selected. The over current threshold and mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be within its intentional value range for either CB3C operation or Latched OC operation.
OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC threshold.
OC_ADJ Resistor Value | Protection Mode | OC Threshold |
---|---|---|
22kΩ | CB3C | 16.3A |
24kΩ | CB3C | 15.1A |
27kΩ | CB3C | 13.5A |
30kΩ | CB3C | 12.3A |
47kΩ | Latched OC | 16.3A |
51kΩ | Latched OC | 15.1A |
56kΩ | Latched OC | 13.5A |
64kΩ | Latched OC | 12.3A |
The output DC protection scheme protects a connected speaker from excess DC current caused by a speaker wire accidentally shorted to chassis ground. Such a short circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current levels. The output DC protection detects any unbalance of the output and input current of a BTL output, and in the event of the unbalance exceeding a programmed threshold, the overload counter increments until its maximum value and the affected output channel is shut down. DC Speaker Protection is disabled in PBTL and SE mode operation.
The PPSC detection system protects the device from permanent damage in the case that a power output pin (OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at startup that is, when VDD is supplied, consequently a short to either GND_X or PVDD_X after system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the device will not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes, and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.
TPA3250 has a two-level temperature-protection system that asserts an active-low warning signal (CLIP_OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
The UVP and POR circuits of the TPA3250 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold.
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET (RESET high) if the OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI recommends monitoring the OTW signal using the system micro controller and responding to an over temperature warning signal by, that is, turning down the volume to prevent further heating of the device resulting in device shutdown (OTE).
Fault/Event | Fault/Event Description | Global or Channel | Reporting Method | Latched/Self Clearing | Action needed to Clear | Output FETs |
---|---|---|---|---|---|---|
PVDD_X UVP | Voltage Fault | Global | FAULT pin | Self Clearing | Increase affected supply voltage | HI-Z |
VDD UVP | ||||||
AVDD UVP | ||||||
POR (DVDD UVP) | Power On Reset | Global | FAULT pin | Self Clearing | Allow DVDD to rise | HI-Z |
BST_X UVP | Voltage Fault | Channel (Half Bridge) | None | Self Clearing | Allow BST cap to recharge (lowside ON, VDD 12V) | HighSide off |
OTW | Thermal Warning | Global | OTW pin | Self Clearing | Cool below OTW threshold | Normal operation |
OTE | Thermal Shutdown | Global | FAULT pin | Latched | Toggle RESET | HI-Z |
OLP (CB3C>1.7ms) | OC Shutdown | Channel | FAULT pin | Latched | Toggle RESET | HI-Z |
Latched OC (47kΩ<ROC_ADJ<68kΩ) | OC Shutdown | Channel | FAULT pin | Latched | Toggle RESET | HI-Z |
CB3C (22kΩ<ROC_ADJ<30kΩ) | OC Limiting | Channel | None | Self Clearing | Reduce signal level or remove short | Flip state, cycle by cycle at fs/3 |
Stuck at Fault(1) | No OSC_IO activity in Slave Mode | Global | None | Self Clearing | Resume OSC_IO activity | HI-Z |
Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down is complete. Output pull downs are active both in SE mode and BTL mode with RESET low.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables weak pulldown of the half-bridge outputs.
Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of FAULT.