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  • TPS65185x PMIC for E Ink® Vizplex™ Enabled Electronic Paper Display

    • SLVSAQ8G February   2011  – September 2017 TPS65185

      PRODUCTION DATA.  

  • CONTENTS
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  • TPS65185x PMIC for E Ink® Vizplex™ Enabled Electronic Paper Display
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Data Transmission
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up and Power-Up Sequencing
      2. 8.3.2  Dependencies Between Rails
      3. 8.3.3  Soft Start
      4. 8.3.4  Active Discharge
      5. 8.3.5  VPOS/VNEG Supply Tracking
      6. 8.3.6  V3P3 Power Switch
      7. 8.3.7  VCOM Adjustment
        1. 8.3.7.1 Kick-Back Voltage Measurement
        2. 8.3.7.2 Storing the VCOM Power-Up Default Value in Memory
      8. 8.3.8  Fault Handling And Recovery
      9. 8.3.9  Power Good Pin
      10. 8.3.10 Interrupt Pin
      11. 8.3.11 Panel Temperature Monitoring
        1. 8.3.11.1 NTC Bias Circuit
        2. 8.3.11.2 Hot, Cold, and Temperature-Change Interrupts
        3. 8.3.11.3 Typical Application of the Temperature Monitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 SLEEP
      2. 8.4.2 STANDBY
      3. 8.4.3 ACTIVE
      4. 8.4.4 Mode Transitions
        1. 8.4.4.1 SLEEP → ACTIVE
        2. 8.4.4.2 SLEEP → STANDBY
        3. 8.4.4.3 STANDBY → ACTIVE
        4. 8.4.4.4 ACTIVE → STANDBY
        5. 8.4.4.5 STANDBY → SLEEP
        6. 8.4.4.6 ACTIVE → SLEEP
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
    6. 8.6 Register Maps
      1. 8.6.1  Thermistor Readout (TMST_VALUE) Register (address = 0x00h) [reset = N/A]
      2. 8.6.2  Enable (ENABLE) Register (address = 0x01h) [reset = 0h]
      3. 8.6.3  Voltage Adjustment (VADJ) Register (address = 0x02h) [reset = 23h]
      4. 8.6.4  VCOM 1 (VCOM1) Register (address = 0x03h) [reset = 7Dh]
      5. 8.6.5  VCOM 2 (VCOM2) Register (address = 0x04h) [reset = 04h]
      6. 8.6.6  Interrupt Enable 1 (INT_EN1) Register (address = 0x05h) [reset = 7Fh]
      7. 8.6.7  Interrupt Enable 2 (INT_EN2) Register (address = 0x06h) [reset = FFh]
      8. 8.6.8  Interrupt 1 (INT1) Register (address = 0x07h) [reset = 0h]
      9. 8.6.9  Interrupt 2 (INT2) Register (address = 0x08h) [reset = N/A]
      10. 8.6.10 Power-Up Sequence 0 (UPSEQ0) Register (address = 0x09h) [reset = E4h]
      11. 8.6.11 Power-Up Sequence 1 (UPSEQ1) Register (address = 0x0Ah) [reset = 55h]
      12. 8.6.12 Power-Down Sequence 0 (DWNSEQ0) Register (address = 0x0Bh) [reset = 1Eh]
      13. 8.6.13 Power-Down Sequence 1 (DWNSEQ1) Register (address = 0x0Ch) [reset = E0h]
      14. 8.6.14 Thermistor 1 (TMST1) Register (address = 0x0Dh) [reset = 20h]
      15. 8.6.15 Thermistor 2 (TMST2) Register (address = 0x0Eh) [reset = 78h]
      16. 8.6.16 Power Good Status (PG) Register (address = 0x0Fh) [reset = 0h]
      17. 8.6.17 Revision and Version Control (REVID) Register (address = 0x10h) [reset = 45h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

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DATA SHEET

TPS65185x PMIC for E Ink® Vizplex™ Enabled Electronic Paper Display

1 Features

  • Single Chip Power-Management Solution for
    E Ink® Vizplex™ Electronic Paper (E-Paper) Displays
  • Generates Positive and Negative Gates, and Source Driver Voltages and Back-Plane Bias From a Single, Low-Voltage Input Supply
  • Supports 9.7-Inch and Larger Panel Sizes
  • 3-V to 6-V Input Voltage Range
  • Boost Converter for Positive Rail Base
  • Inverting Buck-Boost Converter for Negative Rail Base
  • Two Adjustable LDOs for Source Driver Supply
    • TPS65185 LDO1: 15 V, 120 mA (VPOS)
    • TPS65185 LDO2: –15 V, 120 mA (VNEG)
    • TPS651851 LDO1: 15 V, 200 mA at
      VIN ≥ 3.6 V (VPOS)
    • TPS651851 LDO2: –15 V, 200 mA at
      VIN ≥ 3.6 V (VNEG)
  • Accurate Output Voltage Tracking
    • VPOS – VNEG = ±50 mV
  • Two Charge Pumps for Gate Driver Supply
    • CP1: 22 V, 15 mA (VDDH)
    • CP2: –20 V, 15 mA, (VEE)
  • Adjustable VCOM Driver for Accurate Panel-Backplane Biasing
    • 0 V to –5.11 V
    • ± 1.5% accuracy (±10 mV)
    • 9-Bit Control (10-mV Nominal Step Size)
  • Active Discharge on All Rails
  • Integrated 10-Ω, 3.3-V Power Switch for Disabling System Power Rail to E-Ink Panel

2 Applications

  • Power Supply for Active Matrix E Ink Vizplex Panels
  • Electronic Paper Display (EPD) Power Supplies
  • E-Book Readers
  • Dual-Display Phone and Tablets
  • Application Processors With Integrated or Software Timing Controller (OMAP™)

3 Description

The TPS65185x device is a single-chip power supply designed to for E Ink Vizplex displays used in portable e-reader applications, and the device supports panel sizes up to 9.7 inches and greater. Two high efficiency DC-DC boost converters generate ±16-V rails that are boosted to 22 V and –20 V by two change pumps to provide the gate driver supply for the Vizplex panel. Two tracking LDOs create the ±15-V source driver supplies that support up to 120/200 mA (TPS65185/TPS651851) of output current. All rails are adjustable through the I2C interface to accommodate specific panel requirements.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS65185 RGZ (48) 7.00 mm × 7.00 mm
RSL (48) 6.00 mm × 6.00 mm
TPS651851 RSL (48) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

TPS65185 TPS651851 tps65185x-typical-application-schematic.gif

4 Revision History

Changes from F Revision (June 2017) to G Revision

  • Added the load switch and updated the negative and positive charge pumps in the Typical Application Schematic figureGo
  • Added capacitor connection to the pin description for INT_LDO, VB, VCOM, VCOM_PWR, VDDH_D, VEE_D, VIN, VIN_P, VN, VNEG, VNEG_IN, VPOS, VPOS_IN, VREF in the Pin Functions tableGo
  • Changed the Power-Up and Power-Down Timing Diagram Go
  • Changed the Functional Block DiagramGo
  • Changed the schematic in the Typical Application sectionGo

Changes from E Revision (February 2017) to F Revision

  • Updated pin out drawing to match Pin Functions tableGo

Changes from D Revision (December 2016) to E Revision

  • Changed changed the maximum input voltage for TPS651851 from 5.9 V to 6 VGo
  • Changed the VIN range to the VOUTTOL and VDIFF parameters in the Electrical Characteristics tableGo
  • Changed the Electrostatic Discharge Caution statementGo

Changes from C Revision (August 2015) to D Revision

  • Added TPS651851 device to the data sheetGo
  • Added the input voltage range for TPS651851Go
  • Added TPS651851 LDO1 and LDO2 current limit of 200 mAGo
  • Updated the switch current limit to 2.5 A on DCDC1 for TPS651851 Go
  • Updated the LDO1 ILOAD current limit for TPS651851 Go
  • Updated the LDO1 ILIMIT current limit for TPS651851 Go
  • Updated the LDO2 ILOAD current range for different VIN conditions Go
  • Updated the LDO2 ILIMIT output current limit to different VIN conditionsGo
  • Updated the output voltage range (VDDH_OUT) conditions on charge pump 1 Go
  • Added the ILOAD current range option for TPS651851 on CP1 Go
  • Added the ILOAD current range option for TPS651851 on CP2 Go
  • Added Receiving Notification of Documentation Updates to Device and Documentation Support sectionGo

Changes from B Revision (October 2011) to C Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

5 Description (continued)

Accurate back-plane biasing is provided by a linear amplifier that can be adjusted from 0 V to –5.11 V with 9-bit control through the serial interface; it can source or sink current depending on panel condition. The TPS65185x supports automatic panel kickback voltage measurement, which eliminates the need for manual VCOM calibration in the production line. The measurement result can be stored in non-volatile memory to become the new VCOM power-up default value.

TPS65185 is available in two packages, a 48-pin 7-mm × 7-mm2 VQFN (RGZ) with 0.5-mm pitch, and a 48-pin 6-mm × 6-mm2 VQFN (RSL) with 0.4-mm pitch. The TPS651851 is available in a 48-pin 6-mm × 6-mm2 VQFN (RSL) with 0.4-mm pitch.

6 Pin Configuration and Functions

RGZ Package and RSL Package
48-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND1 8 — Analog ground for general analog circuitry.
AGND2 48 — Reference point to external thermistor and linearization resistor.
DGND 6 — Digital ground. Connect to ground plane.
INT 2 O Open drain interrupt pin (active low).
INT_LDO 7 O Filter pin for 2.7-V internal supply. Connect a 4.7-µF capacitor from this pin to ground.
N/C 11, 13, 20, 38, 39 — Not internally connected.
PBKG 22 — Die substrate. Connect to the VN pin (–16 V) with a short, wide trace. A wide copper trace improves heat dissipation.
PGND1 41 — Power ground for DCDC1.
PGND2 32 — Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps.
PWR_GOOD 23 O Open-drain power good output pin. Pin is pulled low when one or more rails are disabled or not in regulation. DCDC1, DCDC2, and VCOM have no effect on this pin.(1)
PWRUP 21 I Power-up pin. Pull this pin high to power up all output rails.(1)
SCL 17 I Serial interface (I2C) clock input.
SDA 18 I/O Serial interface (I2C) data input/output.
TS 47 I Thermistor input pin. Connect a 10-kΩ NTC thermistor and a 43-kΩ linearization resistor between this pin and AGND.
V3P3 46 O Output pin of 3.3-V power switch.
VB 42 I Feedback pin for boost converter (DCDC1) and supply for VPOS LDO and VDDH charge pump. Connect a 4.7-µF capacitor from this pin to ground.
VB_SW 40 O Boost converter switch out (DCDC1).
VCOM 15 O Filter pin for panel common-voltage driver. Connect a 4.7-µF capacitor from this pin to ground.
VCOM_CTRL 12 I VCOM enable. Pull this pin high to enable the VCOM amplifier. When pin is pulled low and VN is enabled, VCOM discharge is enabled.(3)
VCOM_DIS 14 I Discharge pin for VCOM. Connect to ground to discharge VCOM to ground whenever VCOM is disabled. Leave floating if discharge function is not desired.
VCOM_PWR 16 I Internal supply input pin to VCOM buffer. Connect to the output of DCDC2, and connect a 4.7-µF capacitor from this pin to ground.
VDDH_D 34 O Base voltage output pin for positive charge pump (CP1). Connect a 100-nF capacitor from this pin to ground.
VDDH_DIS 35 I Discharge pin for VDDH. Connect to VDDH to discharge VDDH to ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VDDH_DRV 36 O Driver output pin for positive charge pump (CP1).
VDDH_FB 33 I Feedback pin for positive charge pump (CP1).
VDDH_IN 37 I Input supply pin for positive charge pump (CP1).
VEE_D 30 O Base voltage output pin for negative charge pump (CP2). Connect a 100-nF capacitor from this pin to ground.
VEE_DIS 29 I Discharge pin for VEE. Connect a resistor from VEE _DIS to VEE to discharge VEE to ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VEE_DRV 28 O Driver output pin for negative charge pump (CP2).
VEE_FB 31 I Feedback pin for negative charge pump (CP2).
VEE_IN 27 I Input supply pin for negative charge pump (CP2) (VEE).
VIN 10 I Input power supply to general circuitry. Connect a 10-µF capacitor from this pin to ground.
VIN3P3 45 I Input pin to 3.3-V power switch.
VIN_P 24 I Input power supply to inverting buck-boost converter (DCDC2). Connect a 10-µF capacitor from this pin to ground.
VN 26 I Feedback pin for inverting buck-boost converter (DCDC2) and supply for VNEG LDO and VEE charge pump. Connect a 4.7-µF capacitor from this pin to ground.
VNEG 3 O Negative supply output pin for panel source drivers. Connect a 4.7-µF capacitor from this pin to ground.
VNEG_DIS 9 O Discharge pin for VNEG. Connect to VNEG to discharge VNEG to ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VNEG_IN 4 I Input pin for LDO2 (VNEG). Connect a 4.7-µF capacitor from this pin to ground.
VN_SW 25 O Inverting buck-boost converter switch out (DCDC2).
VPOS 44 O Positive supply output pin for panel source drivers. Connect a 4.7-µF capacitor from this pin to ground.
VPOS_DIS 19 I Discharge pin for VPOS. Connect a resistor from VPOS_DIS to VPOS to discharge VPOS to ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VPOS_IN 43 I Input pin for LDO1 (VPOS). Connect a 4.7-µF capacitor from this pin to ground.
VREF 1 O Filter pin for 2.25-V internal reference to ADC. Connect a 4.7-µF capacitor from this pin to ground.
WAKEUP 5 I Wake up pin (active high). Pull this pin high to wake up from sleep mode. The device accepts I2C commands after WAKEUP pin is pulled high but power rails remain disabled until PWRUP pin is pulled high.(2)
Thermal Pad — — The thermal pad is internally connected to the PBKG pin. Connect the thermal pad to the VN pin with a short, wide trace. A wide copper trace improves heat dissipation. Do not connect the thermal pad to ground.
(1) There will be 0-ns of deglitch for PWRx.
(2) There will be 93.75-µs of deglitch for WAKEUP.
(3) There will be 62.52-µs of deglitch for VCOM_CTRL.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Input voltage at VIN(2), VIN_P, VIN3P3 –0.3 7 V
Ground pins to system ground –0.3 0.3 V
Voltage at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB, VEE_FB, PWR_GOOD, nINT –0.3 3.6 V
Voltage on VB, VB_SW, VPOS_IN, VPOS_DIS, VDDH_IN –0.3 20 V
VDDH_DIS –0.3 30 V
Voltage on VN, VEE_IN, VCOM_PWR, VNEG_DIS, VNEG_IN –20 0.3 V
Voltage from VIN_P to VN_SW –0.3 30 V
Voltage on VCOM_DIS –5 0.3 V
VEE_DIS –30 0.3 V
Peak output current Internally limited mA
Continuous total power dissipation 2 W
TJ Operating junction temperature –10 125 °C
TA Operating ambient temperature(3) –10 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the buck-boost output will help heat dissipated efficiently.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage at VIN, VIN_P, VIN3P3 3 3.7 6 V
Voltage at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB, VEE_FB, PWR_GOOD, nINT 0 3.6 V
TA Operating ambient temperature –10 85 °C
TJ Operating junction temperature –10 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS65185 TPS651851 UNIT
RGZ (VQFN) RSL (VQFN) RSL (VQFN)
48 PINS 48 PINS 48 PINS
RθJA Junction-to-ambient thermal resistance 30 30 30 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.6 16.2 16.2 °C/W
RθJB Junction-to-board thermal resistance 6.6 5.1 5.1 °C/W
ψJT Junction-to-top characterization parameter 0.2 0.2 0.2 °C/W
ψJB Junction-to-board characterization parameter 6.6 5.1 5.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 0.9 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE
VIN Input voltage range 3 3.7 6 V
VUVLO Undervoltage lockout threshold VIN falling 2.9 V
VHYS Undervoltage lockout hysteresis VIN rising 400 mV
INPUT CURRENT
IQ Operating quiescent current into VIN Device switching, no load 5.5 mA
ISTD Operating quiescent current into VIN Device in standby mode 130 µA
ISLEEP Shutdown current Device in sleep mode 3.5 10 µA
INTERNAL SUPPLIES
VINT_LDO Internal supply 2.7 V
CINT_LDO Nominal output capacitor Capacitor tolerance ±10% 1 4.7 µF
VREF Internal supply 2.25 V
CREF Nominal output capacitor Capacitor tolerance ±10% 3.3 4.7 µF
DCDC1 (POSITIVE BOOST REGULATOR)
VIN Input voltage range 3 3.7 6 V
PG Power good threshold Fraction of nominal output voltage 90%
Power good time-out Not tested in production 50 ms
VOUT Output voltage range 16 V
DC set tolerance –4.5% 4.5%
IOUT Output current 250 mA
RDS(ON) MOSFET on resistance VIN = 3.7 V 350 mΩ
ILIMIT Switch current limit (TPS65185) 1.5 A
Switch current limit (TPS651851) 2.5
Switch current accuracy –30% 30%
fSW Switching frequency 1 MHz
LDCDC1 Inductor 2.2 µH
CDCDC1 Nominal output capacitor Capacitor tolerance ±10% 1 2 × 4.7 µF
ESR Output capacitor ESR 20 mΩ
DCDC2 (INVERTING BUCK-BOOST REGULATOR)
VIN Input voltage range 3 3.7 6 V
PG Power good threshold Fraction of nominal output voltage 90%
Power good time-out Not tested in production 50 ms
VOUT Output voltage range –16 V
DC set tolerance –4.5% 4.5%
IOUT Output current 250 mA
RDS(ON) MOSFET on resistance VIN = 3.7 V 350 mΩ
ILIMIT Switch current limit 1.5  A
Switch current accuracy –30% 30%
LDCDC1 Inductor 4.7 µH
CDCDC1 Nominal output capacitor Capacitor tolerance ±10% 1 3 × 4.7 µF
ESR Capacitor ESR 20 mΩ
LDO1 (VPOS)
VPOS_IN Input voltage range 15.2 16 16.8 V
PG Power good threshold Fraction of nominal output voltage 90%
Power good time-out Not tested in production 50 ms
VSET Output voltage set value VIN = 16 V,
VSET[2:0] = 0x3h to 0x6h		 14.25 15 V
VINTERVAL Output voltage set resolution VIN = 16 V 250 mV
VOUTTOL Output tolerance VSET = 15 V, ILOAD = 20 mA, 3 V ≤ VIN < 5.9 V –1% 1%
VDROPOUT Dropout voltage ILOAD = 120 mA 250 mV
VLOADREG Load regulation – DC ILOAD = 10% to 90% 1%
ILOAD Load current range (TPS65185) VIN ≥ 3 V 120 mA
Load current range (TPS651851) 3 V ≤ VIN < 3.6 V 150
VIN ≥ 3.6 V 200
ILIMIT Output current limit (TPS65185) VIN ≥ 3 V 120 mA
Output current limit (TPS651851) 3 V ≤ VIN < 3.6 V 150
VIN ≥ 3.6 V 200
RDIS Discharge impedance to ground Enabled when rail is disabled 800 1000 1200 Ω
Mismatch to any other RDIS –2% 2%
CLDO1 Nominal output capacitor Capacitor tolerance ±10% 1 4.7 µF
LDO2 (VNEG)
VNEG_IN Input voltage range 15.2 16 16.8 V
PG Power good threshold Fraction of nominal output voltage 90%
Power good time-out Not tested in production 50 ms
VSET Output voltage set value VIN = –16 V
VSET[2:0] = 0x3h to 0x6h		 –15 –14.25 V
VINTERVAL Output voltage set resolution VIN = –16 V 250 mV
VOUTTOL Output tolerance VSET = –15 V, ILOAD = –20 mA –1% 1%
VDROPOUT Dropout voltage ILOAD = 120 mA 250 mV
VLOADREG Load regulation – DC ILOAD = 10% to 90% 1%
ILOAD Load current range 3 V ≤ VIN < 3.6 V (TPS65185 and TPS651851) 120 mA
VIN ≥ 3.6 V (TPS65185 and TPS651851) 200
ILIMIT Output current limit 3 V ≤ VIN < 3.6 V (TPS65185) 180 mA
3 V ≤ VIN < 3.6 V (TPS651851) 158
VIN ≥ 3.6 V (TPS65185 and TPS651851) 200
RDIS Discharge impedance to ground Enabled when rail is disabled 800 1000 1200 Ω
Mismatch to any other RDIS –2% 2%
TSS Soft-start time Not tested in production 1 ms
CLDO2 Nominal output capacitor Capacitor tolerance ±10% 1 4.7 µF
LD01 (POS) AND LDO2 (VNEG) TRACKING
VDIFF Difference between VPOS and VNEG VSET = ±15 V,
ILOAD = ±20 mA, 0°C to 60°C ambient, 3 V ≤ VIN < 5.9 V		 –50 50 mV
VCOM DRIVER
IVCOM Drive current 15 mA
VCOM Allowed operating range Outside this range VCOM is shut down and VCOMF interrupt is set –5.5 1 V
Accuracy VCOM[8:0] = 0x07Dh
(–1.25 V), VIN = 3.4 V to 4.2 V, no load 		–0.8% 0.8%
VCOM[8:0] = 0x07Dh
(–1.25 V), VIN = 3 V to 6 V, no load 		–1.5% 1.5%
Output voltage range –5.11 0 V
Resolution 1LSB 10 mV
Max number of EEPROM writes VCOM calibration 100
RIN Input impedance, HiZ state HiZ = 1 150 MΩ
RDIS Discharge impedance to ground VCOM_CTRL = low, Hi-Z = 0 800 1000 1200 Ω
Mismatch to any other RDIS –2% 2%
CVCOM Nominal output capacitor Capacitor tolerance ±10% 3.3 4.7 µF
CP1 (VDDH) CHARGE PUMP
VDDH_IN Input voltage range 15.2 16 16.8 V
PG Power good threshold Fraction of nominal output voltage 90%
Power good time-out Not tested in production 50 ms
VFB Feedback voltage 0.998 V
Accuracy ILOAD = 2 mA –2% 2%
VDDH_OUT Output voltage range VSET = 22 V, ILOAD = 2 mA, R6 = 1MΩ, R10 = 47.5 kΩ 21 22 23 V
VSET = 25 V, ILOAD = 2 mA, R6 = 1MΩ, R10 = 41.6 kΩ 24 25 26
VSET = 28 V, ILOAD = 2 mA, R6 = 1MΩ, R10 = 37 kΩ 27 28 29
ILOAD Load current range (TPS65185) 10 mA
Load current range (TPS651851) 15
fSW Switching frequency 560 kHz
RDIS Discharge impedance to ground Enabled when rail is disabled 800 1000 1200 Ω
Mismatch to any other RDIS –2% 2%
CD Driver capacitor 10 nF
CO Output capacitor 1 2.2 µF
CP2 (VEE) NEGATIVE CHARGE PUMP
VEE_IN Input voltage range 15.2 16 16.8 V
PG Power good threshold Fraction of nominal output voltage 90%
Power good time-out Not tested in production 50 ms
VFB Feedback voltage –0.994 V
Accuracy ILOAD = 2 mA –2% 2%
VEE_OUT Output voltage range VSET = –20 V, ILOAD = 3 mA –21 –20 –19 V
ILOAD Load current range (TPS65185) 12 mA
Load current range (TPS651851) 15
fSW Switching frequency 560 kHz
RDIS Discharge impedance to ground Enabled when rail is disabled 800 1000 1200 Ω
Mismatch to any other RDIS –2% 2%
CD Driver capacitor 10 nF
CO Nominal output capacitor Capacitor tolerance ±10% 1 2.2 µF
THERMISTOR MONITOR(1)
ATMS Temperature to voltage ratio Not tested in production –0.0161 V/°C
OffsetTMS Offset Temperature = 0°C 1.575 V
VTMS_HOT Temp hot trip voltage (T = 50°C) TEMP_HOT_SET = 0x8C 0.768 V
VTMS_COOL Temp hot escape voltage (T = 45°C) TEMP_COOL_SET = 0x82 0.845 V
VTMS_MAX Maximum input level 2.25 V
RNTC_PU Internal pullup resistor 7.307 kΩ
RLINEAR External linearization resistor 43 kΩ
ADCRES ADC resolution Not tested in production, 1 bit 16.1 mV
ADCDEL ADC conversion time Not tested in production 19 µs
TMSTTOL Accuracy Not tested in production –1 1 LSB
LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, PWR_GOOD, PWRx, WAKEUP)
VOL Output low threshold level IO = 3 mA, sink current
(SDA, nINT, PWR_GOOD)		 0.4 V
VIL Input low threshold level 0.4 V
VIH Input high threshold level 1.2 V
I(bias) Input bias current VIO = 1.8 V 1 µA
tdeglitch Deglitch time, WAKEUP pin Not tested in production 500 µs
Deglitch time, PWRUP pin Not tested in production 400
tdischarge Discharge delay Not tested in production 100(2) ms
fSCL SCL clock frequency 400 kHz
I2C slave address 7-bit address 0 × 68h(3)
OSCILLATOR
fOSC Oscillator frequency 9 MHz
Frequency accuracy TA = –40°C to 85°C –10% 10%
THERMAL SHUTDOWN
TSHTDWN Thermal trip point 150 °C
Thermal hysteresis 20 °C
(1) 10-kΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 kΩ, 1%) are used at TS pin for panel temperature measurement.
(2) Contact factory for 50-ms, 200-ms or 400-ms option.
(3) Contact TI for alternate address of 0 × 48h.

7.6 Timing Requirements: Data Transmission

VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted)
MIN NOM MAX UNIT
f(SCL) Serial clock frequency 100 400 kHz
tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. SCL = 100 kHz 4 µs
SCL = 400 kHz 600 ns
tLOW LOW period of the SCL clock SCL = 100 kHz 4.7 µs
SCL = 400 kHz 1.3
tHIGH HIGH period of the SCL clock SCL = 100 kHz 4 µs
SCL = 400 kHz 600 ns
tSU;STA Set-up time for a repeated START condition SCL = 100 kHz 4.7 µs
SCL = 400 kHz 600 ns
tHD;DAT Data hold time SCL = 100 kHz 0 3.45 µs
SCL = 400 kHz 0 900 ns
tSU;DAT Data set-up time SCL = 100 kHz 250 ns
SCL = 400 kHz 100
tr Rise time of both SDA and SCL signals SCL = 100 kHz 1000 ns
SCL = 400 kHz 300
tf Fall time of both SDA and SCL signals SCL = 100 kHz 300 ns
SCL = 400 kHz 300
tSU;STO Set-up time for STOP condition SCL = 100 kHz 4 µs
SCL = 400 kHz 600 ns
tBUF Bus Free Time Between Stop and Start Condition SCL = 100 kHz 4.7 µs
SCL = 400 kHz 1.3
tSP Pulse width of spikes that must be suppressed by the input filter SCL = 100 kHz n/a n/a ns
SCL = 400 kHz 0 50
Cb Capacitive load for each bus line SCL = 100 kHz 400 pF
SCL = 400 kHz 400
TPS65185 TPS651851 i2c_data_transmission_lvsaq8.gif Figure 1. I2C Data Transmission Timing
TPS65185 TPS651851 tps65185x-power-up-and-power-down-timing-diagram.gif
1. Minimum delay time between WAKEUP rising edge and IC ready to accept I2C transaction.
2. The device does not enter the SLEEP state until the final discharge delay time has elapsed.

NOTE:

In this example, the first power-up sequence is started by pulling the PWRUP pin high (rising edge). Power-down is initiated by pulling the WAKEUP pin low (device enters sleep mode after rails are discharged). The second power-up sequence is initiated by pulling the WAKEUP pin high while the PWRUP pin is also high (power up from sleep to active).
Figure 2. Power-Up and Power-Down Timing Diagram

7.7 Typical Characteristics

TPS65185 TPS651851 dflt_pwrup_lvsaq8.gif
Figure 3. Default Power-Up Sequence
TPS65185 TPS651851 inrush_3v_lvsaq8.gif
VIN = 3.7 V CIN = 100 µF
Figure 5. Inrush Current
TPS65185 TPS651851 switching_vn_lvsaq8.gif
VIN = 3 V RLOAD, VPOS = 330 Ω RLOAD, VNEG = 330 Ω
No Load on VDDH, VEE
Figure 7. Switching Waveforms, VN
TPS65185 TPS651851 switching_vn2_lvsaq8.gif
VIN = 3.7 V RLOAD, VPOS = 330 Ω RLOAD, VNEG = 330 Ω
No Load on VDDH, VEE
Figure 9. Switching Waveforms, VN
TPS65185 TPS651851 switching_vn3_lvsaq8.gif
VIN = 5 V RLOAD, VPOS = 330 Ω RLOAD, VNEG = 330 Ω
No Load on VDDH, VEE
Figure 11. Switching Waveforms, VN
TPS65185 TPS651851 3p3v_swtch_imp_lvsaq8.gif
VIN = 3.7 V ILOAD, V3p3 = 10 mA
Figure 13. 3p3V Switch Impedance
TPS65185 TPS651851 vcom_int_nonlin_lvsaq8.gif
VIN = 3.7 V RLOAD, VCOM = 1 kΩ
Figure 15. VCOM Integrated Non-Linearity
TPS65185 TPS651851 kickback_error_lvsaq8.gif
VIN = 3.7 V
Figure 17. Kickback Voltage Measurement Error
TPS65185 TPS651851 kickback_timing2_lvsaq8.gif
VIN = 3.7 V AVG[1:0] = 11 (Eight Measurements)
Time from ACQ Bit Set to ACQC Interrupt Received
Figure 19. Kickback Voltage Measurement Timing
TPS65185 TPS651851 dflt_pwrdwn_lvsaq8.gif
Figure 4. Default Power-Down Sequence
TPS65185 TPS651851 inrush_5v_lvsaq8.gif
VIN = 5 V CIN = 100 µF
Figure 6. Inrush Current
TPS65185 TPS651851 switching_vb_lvsaq8.gif
VIN = 3 V RLOAD, VPOS = 330 Ω RLOAD, VNEG = 330 Ω
No Load on VDDH, VEE
Figure 8. Switching Waveforms, VB
TPS65185 TPS651851 switching_vb2_lvsaq8.gif
VIN = 3.7 V RLOAD, VPOS = 330 Ω RLOAD, VNEG = 330 Ω
No Load on VDDH, VEE
Figure 10. Switching Waveforms, VB
TPS65185 TPS651851 switching_vb3_lvsaq8.gif
VIN = 5 V RLOAD, VPOS = 330 Ω RLOAD, VNEG = 330 Ω
No Load on VDDH, VEE
Figure 12. Switching Waveforms, VB
TPS65185 TPS651851 src_driver_lvsaq8.gif
VIN = 3.7 V
Figure 14. Source Driver Supply Tracking
TPS65185 TPS651851 vcom_diff_nonlin_lvsaq8.gif
VIN = 3.7 V RLOAD, VCOM = 1 kΩ
Figure 16. VCOM Differential Non-Linearity
TPS65185 TPS651851 kickback_timing1_lvsaq8.gif
VIN = 3.7 V AVG[1:0] = 00 (Single Measurement)
Time from ACQ Bit Set to ACQC Interrupt Received
Figure 18. Kickback Voltage Measurement Timing

 
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