デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The TPS7A89 is a dual, low-noise (3.8 µVRMS), low-dropout (LDO) voltage regulator capable of sourcing 2 A per channel with only 400 mV of maximum dropout.
The TPS7A89 provides the flexibility of two independent LDOs and approximately 60% smaller solution size than two single-channel LDOs. Each output is adjustable with external resistors from 0.8 V to 5.2 V. The wide input-voltage range of the TPS7A89 supports operation as low as 1.4 V and up to 6.5 V.
With 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce in-rush current, the TPS7A89 is ideal for powering sensitive analog low-voltage devices [such as voltage-controlled oscillators (VCOs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), high-end processors, and field-programmable gate arrays (FPGAs)].
The TPS7A89 is designed to power noise-sensitive components such as those found in high-speed communication, video, medical, or test and measurement applications. The very low 3.8-µVRMS output noise and wideband PSRR (40 dB at 1 MHz) minimizes phase noise and clock jitter. These features maximize the performance of clocking devices, ADCs, and DACs.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A89 | WQFN (20) | 4.00 mm × 4.00 mm |
PIN | DESCRIPTION | ||
---|---|---|---|
NAME | NO. | I/O | |
EN1 | 20 | I | Enable pin for each channel. These pins turn the regulator on and off. If VENx(1) ≥ VIH(ENx), then the regulator is enabled. If VENx ≤ VIL(ENx), then the regulator is disabled. The ENx pin must be connected to INx if the enable function is not used. |
EN2 | 6 | ||
FB1 | 16 | I | Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FBx to OUTx (as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor can disrupt PGx (power good) functionality. See the Feed-Forward Capacitor (CFFx) and Setting the Output Voltage (Adjustable Operation) sections for more details. |
FB2 | 10 | ||
GND | 3, 13 | — | Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection. |
IN1 | 1, 2 | I | Input supply pin for LDO 1. A 10 µF or greater input capacitor is required. Place the input capacitor as close to the input as possible. |
IN2 | 4, 5 | I | Input supply pin for LDO 2. A 10 µF or greater input capacitor is required. Place the input capacitor as close to the input as possible. |
NR/SS1 | 19 | — | Noise-reduction and soft-start pin for each channel. Connecting an external capacitor between this pin and ground reduces reference voltage noise and also enables the soft-start function. Although not required, a 10 nF or larger capacitor is recommended to be connected from NR/SSx to GND (as close to the pin as possible) to maximize ac performance. See the Noise-Reduction and Soft-Start Capacitor (CNR/SSx) section for more details. |
NR/SS2 | 7 | ||
OUT1 | 14, 15 | O | Regulated output for LDO 1. A 22-μF or larger ceramic capacitor (10 μF or greater of effective capacitance) from OUTx to ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT1 pin to the load. See the Input and Output Capacitor (CINx and COUTx) section for more details. |
OUT2 | 11, 12 | O | Regulated output for LDO 2. A 22-μF or larger ceramic capacitor (10 μF or greater of effective capacitance) from OUTx to ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT2 pin to the load. See the Input and Output Capacitor (CINx and COUTx) section for more details. |
PG1 | 17 | O | Open-drain power-good indicator pins for the LDO 1 and LDO 2 output voltages. A 10-kΩ to 100-kΩ external pullup resistor is required. These pins can be left floating or connected to GND if not used. The use of a feed-forward capacitor can disrupt power-good functionality. See the Feed-Forward Capacitor (CFFx) section for more details. |
PG2 | 9 | ||
SS_CTRL1 | 18 | I | Soft-start control pin for each channel. Connect these pins either to GND or INx to allow normal or fast charging of the NR/SSx capacitor. If a CNR/SSx capacitor is not used, SS_CTRLx must be connected to GND to avoid output overshoot. |
SS_CTRL2 | 8 | ||
Thermal pad | — | Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | INx, PGx, ENx(3) | –0.3 | 7.0 | V |
INx, PGx, ENx (5% duty cycle, pulse duration = 200 µs) | –0.3 | 7.5 | ||
OUTx | –0.3 | VINx + 0.3(2) | ||
SS_CTRLx | –0.3 | VINx + 0.3(2) | ||
NR/SSx, FBx(3) | –0.3 | 3.6 | ||
Current | OUTx(3) | Internally limited | A | |
PGx (sink current into device)(3) | 5 | mA | ||
Temperature | Operating junction, TJ | –55 | 150 | °C |
Storage, Tstg | –55 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VINx | Input supply voltage range | 1.4 | 6.5 | V |
VOUTx | Output voltage range | 0.8 – 1% | 5.2 + 1% | V |
IOUTx | Output current | 0 | 2 | A |
CINx | Input capacitor, each input | 10 | µF | |
COUTx | Output capacitor | 22 | µF | |
CNR/SSx | Noise-reduction capacitor | 1 | µF | |
RPGx | Power-good pullup resistance | 10 | 100 | kΩ |
TJ | Junction temperature range | –40 | 125 | °C |
THERMAL METRIC(1) | TPS7A89 | UNIT | |
---|---|---|---|
RTJ (WQFN) | |||
20 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 33 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 26.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 8.0 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 8.0 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VINx(2) | Input supply voltage range | 1.4 | 6.5 | V | ||
VREF | Reference voltage | 0.8 | V | |||
VUVLOx | Input supply UVLOx | VINx rising | 1.31 | 1.39 | V | |
VUVLOx(HYS) | VUVLOx hysteresis | VINx falling hysteresis | 290 | mV | ||
VOUTx | Output voltage range | 0.8 – 1% | 5.2 + 1% | V | ||
VOUTx accuracy(1) | 0.8 V ≤ VOUTx ≤ 5.2 V, 5 mA ≤ IOUTx ≤ 2 A | –1.0% | 1.0% | |||
ΔVOUTx(ΔVINx) | Line regulation | IOUTx = 5 mA, 1.4 V ≤ VINx ≤ 6.5 V | 0.003 | %/V | ||
ΔVOUTx(ΔIOUTx) | Load regulation | 5 mA ≤ IOUTx ≤ 2 A | 0.03 | %/A | ||
VOSx | Error amplifier offset voltage | TJ = 25°C | –2 | 2 | mV | |
VOS1 – VOS2 | Delta between each channel offset voltage | TJ = 25°C | –2 | 2 | mV | |
VDO | Dropout voltage | 1.8 V ≤ VINx ≤ 4.8 V, IOUTx = 2 A, VFBx = 0.8 V – 3% |
180 | 300 | mV | |
1.4 V ≤ VINx < 1.8 V and 4.8 V < VINx ≤ 5.6 V, IOUTx = 2 A, VFBx = 0.8 V – 3% |
250 | 400 | ||||
ILIM | Output current limit | VOUTx forced at 0.9 × VOUTx(TARGET) | 2.3 | 2.6 | 2.9 | A |
IGND | GND pin current | Both channels enabled, per channel, VINx = 6.5 V, IOUTx = 5 mA |
2.1 | 3.5 | mA | |
Both channels enabled, per channel, VINx = 1.4 V, IOUTx = 2 A |
4 | |||||
ISDN | Shutdown GND pin current | Both channels shutdown, per channel, PGx = (open), VINx = 6.5 V, VENx = 0.4 V |
0.1 | 15 | μA | |
IENx | ENx pin current | VINx = 6.5 V, 0 V ≤ VENx ≤ 6.5 V | –0.2 | 0.2 | μA | |
VIL(ENx) | ENx pin low-level input voltage (device disabled) | 0 | 0.4 | V | ||
VIH(ENx) | ENx pin high-level input voltage (device enabled) | 1.1 | 6.5 | V | ||
ISS_CTRLx | SS_CTRLx pin current | VINx = 6.5 V, 0 V ≤ VSS_CTRLx ≤ 6.5 V | –0.2 | 0.2 | μA | |
VIT(PGx) | PGx pin threshold | For PGx transitioning low with falling VOUTx, expressed as a percentage of VOUTx(TARGET) | 82% | 88.9% | 93% | |
Vhys(PGx) | PGx pin hysteresis | For PGx transitioning high with rising VOUTx, expressed as a percentage of VOUTx(TARGET) | 1% | |||
VOL(PGx) | PGx pin low-level output voltage | VOUTx < VIT(PGx), IPGx = –1 mA (current into device) | 0.4 | V | ||
Ilkg(PGx) | PGx pin leakage current | VOUTx > VIT(PGx), VPGx = 6.5 V | 1 | µA | ||
INR/SSx | NR/SSx pin charging current | VNR/SSx = GND, 1.4 V ≤ VINx ≤ 6.5 V, VSS_CTRLx = GND |
4.0 | 6.2 | 9.0 | µA |
VNR/SSx = GND, 1.4 V ≤ VINx ≤ 6.5 V, VSS_CTRLx = VINx | 65 | 100 | 150 | |||
IFBx | FBx pin leakage current | VINx = 6.5 V, VFBx = 0.8 V | –100 | 100 | nA | |
PSRR | Power-supply rejection ratio | f = 500 kHz, VINx = 3.8 V, VOUTx = 3.3 V, IOUTx = 250 mA, CNR/SSx = 10 nF, CFFx = 10 nF |
40 | dB | ||
Vn | Output noise voltage | BW = 10 Hz to 100 kHz, VINx = 1.8 V, VOUTx = 0.8 V, IOUTx = 1 A, CNR/SSx = 1 µF, CFFx = 100 nF |
3.8 | μVRMS | ||
Noise spectral density | f = 10 kHz, VINx = 1.8 V, VOUTx = 0.8 V, IOUTx = 1 A, CNR/SSx = 10 nF, CFFx = 10 nF |
11 | nV/√Hz | |||
Rdiss | Output active discharge resistance | VENx = GND | 250 | Ω | ||
Tsdx | Thermal shutdown temperature | Shutdown, temperature increasing | 160 | °C | ||
Reset, temperature decreasing | 140 |
VOUTx = 5 V, VINx = 5.5 V, VENx = VINx, IOUTx = 2 A, COUTx = 22 µF, CFFx = 10 nF |
VOUTx = 5 V, VINx = 5.4 V, VENx = VINx, COUTx = 22 µF, CNR/SSx = CFFx = 10 nF |
VINx = VOUTx + 0.4 V, IOUTx = 2.0 A, COUTx = 22 µF, CNR/SSx = CFFx = 10 nF |
VOUTx = 1.8 V, IOUTx = 100 mA, COUTx = 22 µF, CNR/SSx = CFFx = 10 nF |
IOUTx = 2 A, VINx = 5.5 V | ||
VINx = 1.7 V, VOUTx = 1.2 V, IOUTx = 1 A, VRMS BW = 22 Hz to 100 kHz, COUTx = 10 µF, CFFx = 10 nF |
VOUTx = 1.2 V, IOUTx = 1 A, COUTx = 22 µF, CNR/SSx = 10 nF | ||
VOUTx = 1.8 V, IOUTx = 1 A, COUTx = 22 µF, CNR/SSx = 1 µF, BW = 10 Hz to 100 kHz |
VINx = 5.5 V, VOUTx = 5 V, COUTx = 22 µF, CFFx = CNR/SSx = 10 nF, slew rate = 1 A/µs |
VINx = 5.5 V, VOUTx = 5 V, IOUTx = 100 mA to 2 A, COUTx = 22 µF, CFFx = CNR/SSx = 10 nF |
IOUTx = 50 mA |
IOUTx = 5 mA |
Single Channel |
Single Channel |
VINx = VPGx = 6.5 V |
VINx = 1.4 V to 6.5 V to 1.4 V at 2 V/µs, VOUTx = 0.8 V, IOUTx = 1 A, CNR/SSx = CFFx = 10 nF |
VINx = 1.4 V |
VINx = 1.4 V |
VOUTx = 5 V, IOUTx = 2 A, COUTx = 22 µF, CNR/SSx = CFFx = 10 nF |
VOUTx = 5.0 V, VINx = 5.5 V, VENx = VINx, IOUTx = 2 A, COUTx = ceramic, CNR/SSx = CFFx = 10 nF |
IOUTx = 2 A, VINx = 5.5 V | ||
VINx = VOUTx + VDOx(max) + 0.1 V or 1.4 V (whichever is greater), IOUTx = 2 A |
VINx = VOUTx + 1.0 V, IOUTx = 1 A, VRMS BW = 22 Hz to 100 kHz, COUTx = 10 µF, CNR/SSx = CFFx = 10 nF |
VINx = 3.8 V, VOUTx = 3.3 V, IOUTx = 1 A, VRMS BW = 22 Hz to 100 kHz, COUTx = 10 µF, CNR/SSx = 10 nF |
VOUTx = 1.8 V, IOUTx = 1 A, COUTx = 22 µF, CFFx = 0.01 µF, BW = 10 Hz to 100 kHz |
VINx = VOUTx + 0.5 V, IOUTx = 100 mA to 2 A, COUTx = 22 µF, CFFx = CNR/SSx = 10 nF, slew rate = 1 A/µs |
VINx = 5.5 V, VOUTx = 5 V, IOUTx = 100 mA to 2 A, CFFx = CNR/SSx = 10 nF, slew rate = 1 A/µs |
VINx = 1.4 V, VOUTx = 0.8 V | ||
VINx = 3.8 V |
VINx = 5.5 V |
VINx = 1.4 V, Single Channel |
VINx = 1.4 V | ||
VINx = 1.4 V |
The TPS7A89 is a monolithic, dual-channel, low-dropout (LDO) regulator. Each channel is low-noise, high-PSRR, and capable of sourcing a 2-A load with 400 mV of maximum dropout. These features make the device a robust solution to solve many challenging problems in generating a clean, accurate power supply.
The various features for each of the TPS7A89 fully independent LDOs simplify using the device in a variety of applications. As detailed in the Functional Block Diagram section, these features are organized into three categories, as shown in Table 1.
VOLTAGE REGULATION | SYSTEM START-UP | INTERNAL PROTECTION |
---|---|---|
High accuracy | Programmable soft-start | Foldback current limit |
Low-noise, high-PSRR output | Sequencing controls | Thermal shutdown |
Fast transient response | Power-good output |
NOINDENT:
An LDO functions as a class-B amplifier in which the input signal is the internal reference voltage (VREF), as shown in Figure 44. VREF is designed to have a very low-bandwidth at the input to the error amplifier through the use of a low-pass filter (VNR/SSx).
As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO comes from the combination of the output capacitor and pass element. The pass element also presents a high input impedance to the source voltage when operating as a current source. A positive LDO can only source current because of the class-B architecture.
This device achieves a maximum of 1% output voltage accuracy primarily because of the high-precision band-gap voltage (VBG) that creates VREF. The low dropout voltage (VDO) reduces the thermal power dissipation required by the device to regulate the output voltage at a given current level, thereby improving system efficiency. Combined, these features help make this device a good approximation of an ideal voltage source.
This device replaces two stand-alone power-supplies, and also provides load-to-load isolation. The LDOs can also be put in series (cascaded) to achieve even higher PSRR by connecting the output of one channel to the input of the other channel.
NOTE:
VOUTx = VREF × (1 + R1x / R2x).Each LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the output current (load transient) resulting from the LDO high-input impedance and low output-impedance across frequency. This same capability also means that each LDO has a high power-supply rejection-ratio (PSRR) and, when coupled with a low internal noise-floor (Vn), the LDO approximates an ideal power supply in ac (small-signal) and large-signal conditions.
The performance and internal layout of the device minimizes the coupling of noise from one channel to the other channel (crosstalk). Good printed circuit board (PCB) layout minimizes the crosstalk.
The choice of external component values optimizes the small- and large-signal response. The NR/SSx capacitor (CNR/SSx) and feed-forward capacitor (CFFx) easily reduce the device noise floor and improve PSRR; see the Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR performance.
In many different applications, the power-supply output must turn-on within a specific window of time to either ensure proper operation of the load or to minimize the loading on the input supply or other sequencing requirements. Each LDO start-up is well-controlled and user-adjustable, solving the demanding requirements faced by many power-supply design engineers in a simple fashion.
Soft-start directly controls the output start-up time and indirectly controls the output current during start-up (in-rush current).
The external capacitor at the NR/SSx pin (CNR/SSx) sets the output start-up time by setting the rise time of the internal reference (VNR/SSx), as shown in Figure 45. SS_CTRLx provides additional control over the rise time of the internal reference by enabling control over the charging current (INR/SSx) for CNR/SSx. The voltage at the SS_CTRLx pin (VSS_CTRLx) must be connected to ground (GND) or VINx.
Note that if CNR/SSx = 0 nF and the SS_CTRLx pin is connected to VINx, then the output voltage overshoots during start-up.
Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of the high power levels inherent in a PDN, and the variations between all of the supplies. Control of each channel turn-on and turn-off time is set by the specific channel enable circuit (ENx) and undervoltage lockout circuit (UVLOx), as shown in Figure 46 and Table 2.
INPUT VOLTAGE | ENABLE STATUS | LDO STATUS | ACTIVE DISCHARGE | POWER-GOOD |
---|---|---|---|---|
VINx ≥ VUVLOx | ENx = 1 | On | Off | PGx = 1 when VOUTx ≥ VIT(PGx) |
ENx = 0 | Off | On | PGx = 0 | |
VINx < VUVLOx – VHYS | ENx = don't care | Off | On(1) | PGx = 0 |
The enable signal (VENx) is an active-high digital control that enables the LDO when the enable voltage is past the rising threshold (VENx ≥ VIH(ENx)) and disables the LDO when the enable voltage is below the falling threshold (VENx ≤ VIL(ENx)). The exact enable threshold is between VIH(ENx) and VIL(ENx) because ENx is a digital control. In applications that do not use the enable control, connect ENx to VINx.
The UVLOx circuit responds quickly to glitches on VINx and attempts to disable the output of the device if either of these rails collapse.
As a result of the fast response time of the input supply UVLOx circuit, fast and short line transients well below the input supply UVLOx falling threshold (brownouts) can cause momentary glitches during the edges of the transient. These glitches are typical in most LDOs. The local input capacitance prevents severe brown-outs in most applications; see the Undervoltage Lockout (UVLOx) Control section for more details.
When either ENx or UVLOx is low, the device connects a resistor of several hundred ohms from VOUTx to GND, discharging the output capacitance.
Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops below the targeted output voltage. Current flows from the output to the input (reverse current) when VOUTx > VINx, which can cause damage to the device (when VOUTx > VINx + 0.3 V); see the Reverse Current Protection section for more details.
The PGx signal provides an easy solution to meet demanding sequencing requirements because PGx signals when the output nears its nominal value. PGx can be used to signal other devices in a system when the output voltage is near, at, or above the set output voltage (VOUTx(Target)). A simplified schematic is shown in Figure 47.
The PGx signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active high. The power-good circuit sets the PGx pin into a high-impedance state to indicate that the power is good.
Using a large feed-forward capacitor (CFFx) delays the output voltage and, because the power-good circuit monitors the FBx pin, the PGx signal can indicate a false positive. A simple solution to this scenario is to use an external voltage detector device, such as the TPS3780; see the Feed-Forward Capacitor (CFFx) section for more information.
In many applications, fault events can occur that damage devices in the system. Short-circuits and excessive heat are the most common fault events for power supplies. The TPS7A89 implements circuitry for each LDO to protect the device and its load during these events. Continuously operating in these fault conditions or above a junction temperature of 125°C is not recommended because the long-term reliability of the device is reduced.
The internal current limit circuit protects the LDO against short-circuit and excessive load current conditions. The output current decreases (folds back) when the output voltage falls to better protect the device, as described in Figure 20. Each channel features its own independent current limit circuit.
The thermal shutdown circuit protects the LDO against excessive heat in the system, either resulting from current limit or high ambient temperature. Each channel features its own independent thermal shutdown circuit.
The output of the LDO turns off when the LDO temperature (junction temperature, TJ) exceeds the rising thermal shutdown temperature (Tsdx). The output turns on again after TJ decreases below the falling thermal shutdown temperature (Tsdx).
A high power dissipation across the device, combined with a high ambient temperature (TA), can cause TJ to be greater than or equal to Tsdx, triggering the thermal shutdown and causing the output to fall to 0 V. The LDO can cycle on and off when thermal shutdown is reached under these conditions.
Table 3 provides a quick comparison between the regulation and disabled operation.
OPERATING MODE | PARAMETER | |||
---|---|---|---|---|
VINx | ENx | IOUTx | TJ | |
Regulation(1) | VINx > VOUTx(nom) + VDO | VENx > VIH(ENx) | IOUTx < ICLx | TJ < Tsd |
Disabled(2) | VINx < VUVLOx | VENx < VIL(ENx) | — | TJ > Tsd |
The device regulates the output to the targeted output voltage when all the conditions in Table 3 are met.
When disabled, the pass device is turned off, the internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal resistor from the output to ground.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Successfully implementing an LDO in an application depends on the application requirements. This section discusses key device features and how to best implement them to achieve a reliable design.
Each LDO resistor feedback network sets the output voltage, as shown in Figure 48, with an output voltage range of 0.8 V to 5.2 V.
Equation 1 relates the values R1x and R2x to VOUTx(Target) and VFBx. Equation 1 is a rearranged version of Equation 2, simplifying the feedback resistor calculation. The current through the feedback network must be equal to or greater than 5 μA for optimum noise performance and accuracy, as shown in Equation 3.
The input bias current into the error amplifier (feedback pin current, IFBx) and tighter tolerance resistors must be taken into account for optimizing the output voltage accuracy.
Table 4 shows the resistor combinations for several common output voltages using commercially-available, 1% tolerance resistors.
TARGETED OUTPUT VOLTAGE (V) | FEEDBACK RESISTOR VALUES(1) | CALCULATED OUTPUT VOLTAGE (V) | |
---|---|---|---|
R1x (kΩ) | R2x (kΩ) | ||
0.80 | Short | Open | 0.800 |
0.90 | 1.37 | 11.0 | 0.900 |
0.95 | 1.91 | 10.2 | 0.950 |
1.00 | 2.55 | 10.2 | 1.000 |
1.05 | 3.32 | 10.7 | 1.048 |
1.10 | 3.57 | 9.53 | 1.100 |
1.15 | 4.64 | 10.7 | 1.147 |
1.20 | 5.49 | 11.0 | 1.199 |
1.35 | 6.98 | 10.2 | 1.347 |
1.50 | 9.31 | 10.7 | 1.496 |
1.80 | 13.70 | 11.0 | 1.796 |
1.90 | 14.70 | 10.7 | 1.899 |
2.50 | 22.60 | 10.7 | 2.490 |
2.85 | 27.40 | 10.7 | 2.849 |
3.00 | 29.40 | 10.7 | 2.998 |
3.30 | 33.20 | 10.7 | 3.282 |
3.60 | 35.70 | 10.2 | 3.600 |
4.50 | 44.20 | 9.53 | 4.510 |
5.00 | 56.20 | 10.7 | 5.002 |
5.20 | 53.60 | 9.76 | 5.193 |
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output pins. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein account for an effective capacitance derating of approximately 50%, but at higher VINx and VOUTx conditions (that is, VINx = 5.5 V to VOUTx = 5.0 V) the derating can be greater than 50% and must be taken into consideration.
The device is designed and characterized for operation with ceramic capacitors of 22 µF or greater (10 µF or greater of effective capacitance) at each input and output. Locate the input and output capacitors as near as practical to the respective input and output pins to minimize the trace inductance from the capacitor to the device.
Although a feed-forward capacitor (CFFx) from the FBx pin to the OUTx pin is not required to achieve stability, a
10-nF external CFFx optimizes the transient, noise, and PSRR performance. A higher capacitance CFFx can be used; however, the start-up time is longer and the power-good signal can incorrectly indicate that the output voltage is settled. The maximum recommended value is 100 nF.
To ensure proper PGx functionality, the time constant defined by CNR/SSx must be greater than or equal to the time constant from CFFx. For a detailed description, see the Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator application report (SBVA042).
Although a noise-reduction and soft-start capacitor (CNR/SSx) from the NR/SSx pin to GND is not required, CNR/SSx is highly recommended to control the start-up time and reduce the noise-floor of the device. The typical value used is 10 nF, and the maximum recommended value is 10 µF.
Each output of the device features a user-adjustable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CNR/SSx). This soft-start eliminates power-up initialization problems when powering field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, thus minimizing start-up transients to the input power bus.
The output voltage (VOUTx) rises proportionally to VNR/SSx during start-up as the LDO regulates so that the feedback voltage equals the NR/SSx voltage (VFBx = VNR/SSx). As such, the time required for VNR/SSx to reach its nominal value determines the rise time of VOUTx (start-up time).
The soft-start ramp time depends on the soft-start charging current (INR/SSx), the soft-start capacitance (CNR/SSx), and the internal reference (VREF). The approximate soft-start ramp time (tSSx) can be calculated with Equation 4:
The SS_CTRLx pin for each output sets the value of the internal current source, maintaining a fast start-up time even with a large CNR/SSx capacitor. When the SS_CTRLx pin is connected to GND, the typical value for the INR/SSx current is 6.2 µA. Connecting the SS_CTRLx pin to INx increases the typical soft-start charging current to 100 µA. The larger charging current for INR/SSx is useful when smaller start-up ramp times are needed or when using larger noise-reduction capacitors.
Not using a noise-reduction capacitor on the NR/SSx pin and tying the SS_CTRLx pin to VINx results in output voltage overshoot of approximately 10%. Connecting the SS_CTRLx pin to GND or using a capacitor on the NR/SSx pin minimizes the overshoot.
Values for the soft-start charging currents are provided in the Electrical Characteristics table.
In-rush current is defined as the current into the LDO at the INx pin during start-up. In-rush current then consists primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to measure because the input capacitor must be removed, which is not recommended. However, this soft-start current can be estimated by Equation 5:
where
The UVLOx circuit ensures that the device stays disabled before its input or bias supplies reach the minimum operational voltage range, and ensures that the device properly shuts down when the input supply collapses.
Figure 49 and Table 5 explain the UVLOx circuit response to various input voltage events, assuming VENx ≥ VIH(ENx).
REGION | EVENT | VOUTx STATUS | COMMENT |
---|---|---|---|
A | Turn-on, VINx ≥ VUVLOx | 0 | Start-up |
B | Regulation | 1 | Regulates to target VOUTx |
C | Brownout, VINx ≥ VUVLOx – VHYS | 1 | The output can fall out of regulation but the device is still enabled. |
D | Regulation | 1 | Regulates to target VOUTx |
E | Brownout, VINx < VUVLOx – VHYS | 0 | The device is disabled and the output falls because of the load and active discharge circuit. The device is reenabled when the UVLOx rising threshold is reached by the input voltage and a normal start-up then follows. |
F | Regulation | 1 | Regulates to target VOUTx |
G | Turn-off, VINx < VUVLOx – VHYS | 0 | The output falls because of the load and active discharge circuit. |
Similar to many other LDOs with this feature, the UVLOx circuit takes a few microseconds to fully assert. During this time, a downward line transient below approximately 0.8 V causes the UVLOx to assert for a short time; however, the UVLOx circuit does not have enough stored energy to fully discharge the internal circuits inside of the device. When the UVLOx circuit is not given enough time to fully discharge the internal nodes, the outputs are not fully disabled.
The effect of the downward line transient can be mitigated by using a larger input capacitor to increase the fall time of the input supply when operating near the minimum VINx.
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. The power-good circuit asserts whenever FBx, VINx, or ENx are below their thresholds. The PGx operation versus the output voltage is shown in Figure 50, which is described by Table 6.
REGION | EVENT | PGx STATUS | FBx VOLTAGE |
---|---|---|---|
A | Turn-on | 0 | VFBx < VIT(PGx) + VHYS(PGx) |
B | Regulation | Hi-Z | VFBx ≥ VIT(PGx) |
C | Output voltage dip | Hi-Z | |
D | Regulation | Hi-Z | |
E | Output voltage dip | 0 | VFBx < VIT(PGx) |
F | Regulation | Hi-Z | VFBx ≥ VIT(PGx) |
G | Turn-off | 0 | VFBx < VIT(PGx) |
The PGx pin is open-drain and connecting a pullup resistor to an external supply enables others devices to receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices.
To ensure proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor is outside of this range, then the power-good signal may not read a valid digital logic level.
Using a large CFFx with a small CNR/SSx causes the power-good signal to incorrectly indicate that the output voltage has settled during turn-on. The CFFx time constant must be greater than the soft-start time constant to ensure proper operation of the PGx during start-up. For a detailed description, see the Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator application report (SBVA042).
The state of PGx is only valid when the device operates above the minimum supply voltage. During short brownout events and at light loads, power-good does not assert because the output voltage (therefore VFBx) is sustained by the output capacitance.
LDO ac performance for a dual-channel device includes power-supply rejection ratio, channel-to-channel output isolation, output current transient response, and output noise. These metrics are primarily a function of open-loop gain, bandwidth, and phase margin that control the closed-loop input and output impedance of the LDO. The output noise is primarily a result of the reference and error amplifier noise.
PSRR is a measure of how well the LDO control-loop rejects signals from VINx to VOUTx across the frequency spectrum (usually 10 Hz to 10 MHz). Equation 6 gives the PSRR calculation as a function of frequency for the input signal [VINx(f)] and output signal [VOUTx(f)].
Even though PSRR is a loss in signal amplitude, PSRR is shown as positive values in decibels (dB) for convenience.
A simplified diagram of PSRR versus frequency is shown in Figure 51.
An LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply voltages that exhibit ultra-low noise and ripple to sensitive system components. This usage is especially true for the TPS7A89.
The TPS7A89 features an innovative circuit to boost the PSRR between 200 kHz and 1 MHz; see Figure 3. To achieve the maximum benefit of this PSRR boost circuit, using a capacitor with a minimum impedance in the 100-kHz to 1-MHz band is recommended.
Output isolation is a measure of how well the device prevents voltage disturbances on one output from affecting the other output. This attenuation appears in load transient tests on the other output; however, to numerically quantify the rejection, the output channel isolation is expressed in decibels (dB).
Output isolation performance is a strong function of the PCB layout. See the Layout section on how to best optimize the isolation performance.
The TPS7A89 is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. For example, the TPS7A89 can be used in a phase-locked loop (PLL)-based clocking circuit can be used for minimum phase noise, or in test and measurement systems where even small power-supply noise fluctuations reduce system dynamic range.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions, thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower frequencies as a function of 1/f). Figure 52 shows a simplified output voltage noise density plot versus frequency.
For further details, see the How to Measure LDO Noise white paper (SLYY076).
The ultra-low noise floor and PSRR of the device can be improved in several ways, as described in Table 7.
PARAMETER | NOISE | PSRR | ||||
---|---|---|---|---|---|---|
LOW-FREQUENCY | MID-FREQUENCY | HIGH-FREQUENCY | LOW-FREQUENCY | MID-FREQUENCY | HIGH-FREQUENCY | |
CNR/SSx | +++ | No effect | No effect | +++ | + | No effect |
CFFx | ++ | +++ | + | ++ | +++ | + |
COUTx | No effect | + | +++ | No effect | + | +++ |
VINx – VOUTx | + | + | + | +++ | +++ | ++ |
PCB layout | ++ | ++ | + | + | +++ | +++ |
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that filters out the noise from the reference before being gained up with the error amplifier, thereby minimizing the output voltage noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with Equation 7. The typical value of RNR is 250 kΩ. The effect of the CNR/SSx capacitor increases when VOUTx(Target) increases because the noise from the reference is gained up when the output voltage increases. For low-noise applications, a 10-nF to 10-µF CNR/SSx is recommended.
The feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. The feed-forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing out the loop bandwidth, thus improving mid-band PSRR.
A larger COUTx or multiple output capacitors reduces high-frequency output voltage noise and PSRR by reducing the high-frequency output impedance of the power supply.
Additionally, a higher input voltage improves the noise and PSRR because greater headroom is provided for the internal circuits. However, a high power dissipation across the die increases the output noise because of the increase in junction temperature.
Good PCB layout improves the PSRR and noise performance by providing heatsinking at low frequencies and isolating VOUTx at high frequencies.
Table 8 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5-V output for a variety of conditions with an input voltage of 5.5 V, an R1x of 12.1 kΩ, and a load current of 2 A. The 5-V output is chosen because this output is the worst-case condition for output voltage noise.
CNR/SSx (nF) | CFFx (nF) | COUTx (µF) | SS_CTRLx | OUTPUT VOLTAGE NOISE (µVRMS) |
---|---|---|---|---|
10 | 10 | 22 | VINx | 11.3 |
1000 | 100 | 22 | VINx | 6.1 |
1000 | 100 | 22 | GND | 6.1 |
1000 | 100 | 22 || 1000 | VINx | 6 |
The device internal charge pump generates a minimal amount of noise.
The high-frequency components of the output voltage noise density curve are filtered out in most applications by using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure 53 are broken down in this section and are described in Table 9. Regions A, E, and H are where the output voltage is in steady-state.
REGION | DESCRIPTION | COMMENT |
---|---|---|
A | Regulation | Regulation |
B | Output current ramping | Initial voltage dip is a result of the depletion of the output capacitor charge. |
C | LDO responding to transient | Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation. |
D | Reaching thermal equilibrium | At high load currents the LDO takes some time to heat up. During this time the output voltage changes slightly. |
E | Regulation | Regulation |
F | Output current ramping | Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase. |
G | LDO responding to transient | Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor. |
H | Regulation | Regulation |
The transient response peaks (VOUTx(max) and VOUTx(min)) are improved by using more output capacitance; however, doing so slows down the recovery time (Wrise and Wfall). Figure 54 shows these parameters during a load transient, with a given pulse duration (PW) and current levels (IOUTx(LO) and IOUTx(HI)).
The device features an output voltage accuracy of 1% maximum that includes the errors introduced by the internal reference, load regulation, line regulation, and operating temperature as specified by the Electrical Characteristics table. Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal output voltage stated as a percent.
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and output voltage (VDO = VINx – VOUTx) that is required for regulation. When VINx drops below the required VDO for the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is proportional to the output current because the device is operating as a resistive switch, as shown in Figure 55.
Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect to VINx on this device because of the internal charge pump. Dropout voltage increases exponentially when the input voltage nears its maximum operating voltage because the charge pump multiplies the input voltage by a factor of 4 and then is internally clamped to 8.0 V.
Some applications can have transients that place the LDO into dropout, such as slower ramps on VINX for start-up or load transients. As with many other LDOs, the output can overshoot on recovery from these conditions.
A ramping input supply can cause an LDO to overshoot on start-up when the slew rate and voltage levels are in the right range, as shown in Figure 56. This condition is easily avoided through either the use of an enable signal, or by increasing the soft-start time with CSS/NRx.
As with most LDOs, this device can be damaged by excessive reverse current.
Reverse current is current that flows through the body diode on the pass element instead of the normal conducting channel. This current flow, at high enough magnitudes, degrades long-term reliability of the device resulting from risks of electromigration and excess heat being dissipated across the device. If the current flow gets high enough, a latch-up condition can be entered.
Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUTx > VINx + 0.3 V:
Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. PD can be approximated using Equation 8:
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (θJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to Equation 9. The equation is rearranged for output current in Equation 10.
Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The θJA recorded in the table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. Note that for a well-designed thermal layout, θJA is actually the sum of the VQFN package junction-to-case (bottom) thermal resistance (θJCbot) plus the thermal resistance contribution by the PCB copper.
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are given in the table and are used in accordance with Equation 11.
where
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input voltage. The recommended area for continuous operation for a linear regulator can be separated into the following parts, and is shown in Figure 58:
Figure 59 to Figure 64 show the recommended area of operation curves for this device on a JEDEC-standard, high-K board with a θJA = 35.4°C/W, as given in the table.
This section discusses the implementation of the TPS7A89 to regulate from a common input voltage to two output voltages of the same value. This application is common for when two noise-sensitive loads must have the same supply voltage but have high channel-to-channel isolation. The schematic for this application circuit is provided in Figure 65.
For the design example shown in Figure 65, use the parameters listed in Table 10 as the input parameters.
PARAMETER | DESIGN REQUIREMENT |
---|---|
Input voltages (VIN1 and VIN2) | 3.7 V, ±1%, provided by the dc-dc converter switching at 750 kHz |
Maximum ambient operating temperature | 85°C |
Output voltages (VOUT1 and VOUT2) | 3.3 V, ±1%, output voltages are isolated |
Output currents (IOUT2 and IOUT2) | 2 A (maximum), 100 mA (minimum) |
Channel-to-channel isolation | Isolation greater than 50 dB at 100 kHz |
RMS noise | < 5 µVRMS, bandwidth = 10 Hz to 100 kHz |
PSRR at 750 kHz | > 40 dB |
Startup time | < 5 ms |
The output voltages can be set to 1.2 V by selecting the correct values for R1x and R2x; see Equation 1.
Input and output capacitors are selected in accordance with the External Component Selection section. Ceramic capacitances of 10 µF for both inputs and outputs are selected.
To minimize noise, a feed-forward capacitance (CFFx) of 10 nF is selected.
Channel-to-channel isolation depends greatly on the layout of the design. To minimize crosstalk between the outputs, keep the output capacitor grounds on separate sides of the design. See the Layout section for an example of how to layout the TPS7A89 to achieve best PSRR, channel-to-channel isolation, and noise.
IOUTx = 2 A |
Both inputs of the TPS7A89 are designed to operate from an input voltage range between 1.4 V and 6.5 V. The input voltage range must provide adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy or has a high output impedance, additional input capacitors with low ESR can help improve the output noise performance.