The UCC28720 flyback power supply controller provides isolated-output Constant-Voltage (CV) and Constant-Current (CC) output regulation without the use of an optical coupler. The devices process information from the primary power switch and an auxiliary flyback winding for precise control of output voltage and current.
An internal 700-V start-up switch, dynamically-controlled operating states and a tailored modulation profile support ultra-low standby power without sacrificing start-up time or output transient response.
Control algorithms in the UCC28720 allow operating efficiencies to meet or exceed applicable standards. The output drive interfaces to a bipolar transistor power switch. Discontinuous conduction mode (DCM) with valley switching reduces switching losses. Modulation of switching frequency and primary current peak amplitude (FM and AM) keeps the conversion efficiency high across the entire load and line ranges.
The controller has a maximum switching frequency of 80 kHz and always maintains control of the peak-primary current in the transformer. Protection features help keep primary and secondary component stresses in check. The UCC28720 allows compensation for voltage drop in the cable to be programmed with an external resistor.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCC28720 | SOIC (7) | 3.91 mm × 4.90 mm |
Changes from A Revision (January 2014) to B Revision
Changes from * Revision (May 2014) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
VDD | 1 | I | VDD is the bias supply input pin to the controller. A carefully-placed bypass capacitor to GND is required on this pin. |
VS | 2 | I | Voltage sense is an input used to provide voltage and timing feedback to the controller. This pin is connected to a voltage divider between an auxiliary winding and GND. The value of the upper resistor of this divider is used to program the AC-mains run and stop thresholds and line compensation at the CS pin. |
CBC | 3 | I | Cable compensation is a programming pin for compensation of cable voltage drop. Cable compensation is programmed with a resistor to GND. |
GND | 4 | — | The ground pin is both the reference pin for the controller and the low-side return for the drive output. Special care must be taken to return all AC decoupling capacitors as close as possible to this pin and avoid any common trace length with analog signal return paths. |
CS | 5 | I | Current sense input connects to a ground-referenced current-sense resistor in series with the power switch. The resulting voltage is used to monitor and control the peak primary current. A series resistor can be added to this pin to compensate the peak switch current levels as the AC-mains input varies. |
DRV | 6 | O | Drive is an output used to drive the base of an external high voltage NPN transistor. |
HV | 7 | I | The high-voltage pin connects directly to the rectified bulk voltage and provides charge to the VDD capacitor for start-up of the power supply. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VHV | Start-up pin voltage, HV | 700 | V | |
VVDD | Bias supply voltage, VDD | 38 | V | |
IDRV | Continuous base current sink | 50 | mA | |
IDRV | Continuous base current source | Self- limiting | mA | |
IVS | Peak current, VS | −1.2 | mA | |
VDRV | Base drive voltage at DRV | −0.5 | Self- limiting | V |
VS | Voltage | −0.75 | 7 | V |
CS, CBC | −0.5 | 5 | V | |
TJ | Operating junction temperature | −55 | 150 | °C |
Lead temperature 0.6 mm from case for 10 seconds | 260 | °C | ||
TSTG | Storage temperature | −65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDD | Bias supply operating voltage | 9 | 35 | V | |
CVDD | VDD bypass capacitor | 1.0 | 10 | µF | |
RCBC | Cable-compensation resistance | 10 | kΩ | ||
IVS | VS pin current | −1 | mA | ||
TJ | Operating junction temperature | −40 | 125 | °C |
THERMAL METRIC(1) | UCC28720 | UNIT | |
---|---|---|---|
D (SOIC) | |||
7 PIN | |||
RθJA | Junction-to-ambient thermal resistance | 141.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 73.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 89.0 | °C/W |
ψJT | Junction-to-top characterization parameter | 23.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 88.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
HIGH-VOLTAGE START UP | |||||||
IHV | Start-up current out of VDD | VHV = 100 V, VVDD = 0 V, start state | 100 | 225 | 500 | µA | |
IHVLKG | Leakage current at HV | VHV = 400 V, run state, TJ = 25 ºC | 0.01 | 0.25 | µA | ||
BIAS SUPPLY INPUT | |||||||
IRUN | Supply current, run | IDRV = 0, run state | 2.00 | 2.65 | mA | ||
IWAIT | Supply current, wait | IDRV = 0, wait state | 95 | 150 | µA | ||
ISTART | Supply current, start | IDRV = 0, VVDD = 18 V, start state, IHV = 0 | 18 | 30 | µA | ||
IFAULT | Supply current, fault | IDRV = 0, fault state | 95 | 150 | µA | ||
UNDERVOLTAGE LOCKOUT | |||||||
VVDD(on) | VDD turn-on threshold | VVDD low to high | 19 | 21 | 23 | V | |
VVDD(off) | VDD turn-off threshold | VVDD high to low | 7.35 | 7.7 | 8.15 | V | |
VS INPUT | |||||||
VVSR | Regulating level | Measured at no-load condition, TJ = 25°C(1) | 4.01 | 4.05 | 4.09 | V | |
V | |||||||
VVSNC | Negative clamp level | IVS = -300 µA, volts below ground | 190 | 250 | 325 | mV | |
IVSB | Input bias current | VVS = 4 V | -0.25 | 0 | 0.25 | µA | |
CS INPUT | |||||||
VCST(max) | Max CS threshold voltage | VVS = 3.7 V | 735 | 780 | 815 | mV | |
VCST(min) | Min CS threshold voltage | VVS = 4.35 V | 175 | 190 | 215 | mV | |
KAM | AM control ratio | VCST(max) / VCST(min) | 3.6 | 4.0 | 4.4 | V/V | |
VCCR | Constant current regulating level | CC regulation constant | 317 | 330 | 344 | mV | |
KLC | Line compensation current ratio | IVSLS = -300 µA, IVSLS / current out of CS pin | 24.0 | 25.0 | 28.6 | A/A | |
TCSLEB | Leading-edge blanking time | DRV output duration, V CS = 1 V | 230 | 290 | 355 | ns | |
DRIVER | |||||||
IDRS(max) | Maximum DRV source current | VDRV = 2 V, VVDD = 9 V, VVS = 3.85 V | 32 | 37 | 41 | mA | |
IDRS(min) | Minimum DRV source current | VDRV = 2 V, VVDD = 9 V, VVS = 4.30 V | 16 | 19 | 22 | mA | |
RDRVLS | DRV low-side drive resistance | IDRV = 10 mA | 1 | 2.4 | Ω | ||
VDRCL | DRV clamp voltage | VVDD = 35 V | 5.9 | 7 | V | ||
RDRVSS | DRV pull-down in start state | 20 | 25 | kΩ | |||
VOVP | Over-voltage threshold | At VS input, TJ = 25°C(1) | 4.51 | 4.60 | 4.73 | V | |
V | |||||||
VOCP | Over-current threshold | At CS input | 1.4 | 1.5 | 1.6 | V | |
IVSL(run) | VS line-sense run current | Current out of VS pin increasing | 190 | 225 | 275 | µA | |
IVSL(stop) | VS line-sense stop current | Current out of VS pin decreasing | 70 | 80 | 100 | µA | |
KVSL | VS line sense ratio | IVSL(run) / IVSL(stop) | 2.45 | 2.80 | 3.05 | A/A | |
TJ(stop) | Thermal shut-down temperature | Internal junction temperature | 165 | °C | |||
CABLE COMPENSATION | |||||||
VCBC(max) | Cable compensation maximum voltage | Voltage at CBC at full load | 2.9 | 3.1 | 3.5 | V | |
VCVS(min) | Minimum compensation at VS | VCBC = open, change in VS regulating level at full load | -55 | -15 | 25 | mV | |
VCVS(max) | Maximum compensation at VS | VCBC = 0 V, change in VS regulating level at full load | 275 | 320 | 380 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSW(max) + | Maximum switching frequency | VVS = 3.7 V | 74 | 80 | 87 | kHz |
fSW(min) | Minimum switching frequency | VVS = 4.35 V | 580 | 650 | 740 | Hz |
tZTO | Zero-crossing timeout delay | 2.5 | 3.1 | 3.6 | µs |