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  • AMC1336 小型、高精度、強化絶縁型デルタ-シグマ変調器電圧センシング・アプリケーション用

    • JAJSHR4B August   2019  – April 2020 AMC1336

      PRODUCTION DATA.  

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  • AMC1336 小型、高精度、強化絶縁型デルタ-シグマ変調器電圧センシング・アプリケーション用
  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1.  Absolute Maximum Ratings
    2. Table 2.  ESD Ratings
    3. Table 3.  Recommended Operating Conditions
    4. Table 4.  Thermal Information
    5. Table 5.  Power Ratings
    6. Table 6.  Insulation Specifications
    7. Table 7.  Safety-Related Certifications
    8. Table 8.  Safety Limiting Values
    9. Table 9.  Electrical Characteristics
    10. Table 10. Switching Characteristics
    11. 6.1       Insulation Characteristics Curves
    12. 6.2       Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Clock Input
      5. 7.3.5 Digital Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Behavior in Case of a Full-Scale Input
      2. 7.4.2 AVDD Diagnostics and Fail-Safe Output
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Digital Filter Usage
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
      4. 8.2.4 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デバイスの項目表記
        1. 11.1.1.1 絶縁の用語集
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報
  13. 重要なお知らせ
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DATA SHEET

AMC1336 小型、高精度、強化絶縁型デルタ-シグマ変調器電圧センシング・アプリケーション用

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

  • 電圧測定用に最適化された入力構造
    • 入力電圧範囲：±1V
    • 入力抵抗：1.5GΩ (標準値)
  • 非常に優れた DC 性能
    • オフセット誤差：±0.5mV (最大値)
    • オフセット・ドリフト係数：±4µV/℃ (最大値)
    • ゲイン誤差：±0.25% (最大値)
    • ゲイン・ドリフト係数：±40ppm/℃ (最大値)
  • 過渡耐性：115 kV/µs (標準値)
  • ハイサイド電源喪失の検出
  • 安全関連の認定
    • DIN VDE V 0884-11: 2017-01 に準拠した強化絶縁耐圧：8000VPEAK
    • UL 1577 に準拠した絶縁耐圧：5700VRMS (1 分間)
    • IEC 62368-1 最終機器標準

2 アプリケーション

  • 次の用途での絶縁 AC および DC 電圧測定
    • 無停電電源
    • 太陽光発電インバータ
    • モータ・ドライブ

3 概要

AMC1336 は高精度のデルタ-シグマ (ΔΣ) 変調器で、磁気干渉に対して高い耐性のある二重の静電容量性絶縁バリアを採用して、入力回路と出力回路を電気的に分離しています。この絶縁バリアは、DIN VDE V 0884-11 および UL1577 規格に準拠した、8000VPEAK までの強化絶縁体に認定されています。この絶縁変調器を絶縁電源と組み合わせて使用すると、システムの中で異なる同相電圧レベルで動作する部分が分離され、低電圧部分の損傷を防ぎます。

AMC1336 独自の広いバイポーラの±1V 入力電圧範囲と、高い入力抵抗から、高電圧アプリケーションでデバイスを分圧抵抗に直接接続できます。デジタル・フィルタ (TMS320F28004x、TMS320F2807x、TMS320F2837x マイクロコントローラ・ファミリに内蔵されているものなど) を使用して出力ビットストリームを間引くと、82kSPS のデータ速度、87dB のダイナミック・レンジで、16 ビットの分解能が得られます。


ハイサイドでは、AMC1336 は 3.3V または 5V 電源から給電されます。絶縁デジタル・インターフェイスは、3.0V、3.3V、5V の電源で動作します。

AMC1336 は、-40℃～+125℃の拡張工業用温度範囲で動作が規定されています。

製品情報(1)

型番 パッケージ 本体サイズ（公称）
AMC1336 SOIC (8) 5.85mm×7.50mm
  1. 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。

Device Images

概略回路図

AMC1336 frontpage_bas951.gif

4 改訂履歴

Changes from A Revision (December 2019) to B Revision

  • Changed PD (AVDD = DVDD = 5.5 V) from 88 mW to 90.75 mW.Go
  • Changed PD1 (AVDD = 5.5 V) from 55 mW to 57.75 mWGo
  • Added UL certification file number.Go

Changes from * Revision (August 2019) to A Revision

  • Changed ドキュメント・ステータスを事前情報から量産データにGo

5 Pin Configuration and Functions

DWV Package
8-Pin SOIC
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 AVDD — Analog (high-side) power supply, 3.0 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
2 AINP I Noninverting analog input
3 AINN I Inverting analog input
4 AGND — Analog (high-side) ground reference
5 DGND — Digital (controller-side) ground reference
6 DOUT O Modulator bitstream output, updated with the rising edge of the clock signal present on CLKIN. Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device.
7 CLKIN I Modulator clock input with internal pulldown resistor (typical value: 1 MΩ). The clock signal must be applied continuously for proper device operation; see the Clock Input section for additional details.
8 DVDD — Digital (controller-side) power supply, 2.7 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.

6 Specifications

Table 1. Absolute Maximum Ratings

see(1)
MIN MAX UNIT
Power-supply voltage AVDD to AGND –0.3 6.5 V
DVDD to DGND –0.3 6.5
Analog input voltage On the AINP and AINN pins AGND – 5 AVDD + 0.5 V
Digital input voltage On the CLKIN pin DGND – 0.5 DVDD + 0.5 V
Digital output voltage On the DOUT pin DGND – 0.5 DVDD + 0.5 V
Input current Continuous, any pin except power-supply pins –10 10 mA
Temperature Junction, TJ 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Table 3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Table 2. ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Table 3. Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
AVDD High-side supply voltage AVDD to AGND 3.0 5.0 5.5 V
DVDD Controller-side DVDD to DGND 2.7 3.3 5.5 V
ANALOG INPUT
VClipping Differential input voltage before clipping output VIN = VAINP – VAINN ±1.25 V
VFSR Specified linear differential full-scale voltage VIN = VAINP – VAINN –1 1 V
Absolute common-mode input voltage(1) (VAINP + VAINN) / 2 to AGND –2 AVDD V
VCM Operating common-mode input voltage(2) (VAINP + VAINN) / 2 to AGND,
3.0 V ≤ AVDD < 4 V,
VAINP = VAINN 		–1.4 AVDD – 1.4 V
(VAINP + VAINN) / 2 to AGND,
3.0 V ≤ AVDD < 4.5 V,
|VAINP – VAINN| = 1.25 V		 –0.8 AVDD – 2.4
(VAINP + VAINN) / 2 to AGND,
4 V ≤ AVDD ≤ 5.5 V,
VAINP = VAINN 		–1.4 2.7
(VAINP + VAINN) / 2 to AGND,
4.5 V ≤ AVDD ≤ 5.5 V,
|VAINP – VAINN| = 1.25 V		 –0.8 2.1
DIGITAL INPUT
Input voltage VCLKIN to DGND DGND DVDD V
TEMPERATURE RANGE
TA Operating ambient temperature –40 25 125 °C
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal operation. Observe analog input voltage range as specified in the Table 1 table.
(2) See the Analog Input section for more details.

Table 4. Thermal Information

THERMAL METRIC(1) AMC1336 UNIT
DWV (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance 94 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 36 °C/W
RθJB Junction-to-board thermal resistance 46.1 °C/W
ψJT Junction-to-top characterization parameter 11.5 °C/W
ψJB Junction-to-board characterization parameter 44.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Table 5. Power Ratings

PARAMETER TEST CONDITIONS VALUE UNIT
PD Maximum power dissipation (both sides) AVDD = DVDD = 5.5 V 90.75 mW
AVDD = DVDD = 3.6 V 50.4
PD1 Maximum power dissipation (high-side supply) AVDD = 5.5 V 57.75 mW
AVDD = 3.6 V 32.4
PD2 Maximum power dissipation (controller-side supply) DVDD = 5.5 V 33 mW
DVDD = 3.6 V 18

Table 6. Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air ≥ 8.5 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥ 8.5 mm
DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation ≥ 0.021 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Overvoltage category
per IEC 60664-1		 Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN VDE V 0884-11: 2017-01(2)
VIORM Maximum repetitive peak isolation voltage At AC voltage 2121 VPK
VIOWM Maximum-rated isolation
working voltage		 At AC voltage (sine wave); see Figure 5 1500 VRMS
At DC voltage 2121 VDC
VIOTM Maximum transient
isolation voltage		 VTEST = VIOTM, t = 60 s (qualification test) 8000 VPK
VTEST = 1.2 × VIOTM, t = 1 s (100% production test) 9600
VIOSM Maximum surge
isolation voltage(3) 		Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)		 8000 VPK
qpd Apparent charge(4) Method a, after input/output safety test subgroups 2 & 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s		 ≤ 5
Method b1, at routine test (100% production) and preconditioning (type test),
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s		 ≤ 5
CIO Barrier capacitance,
input to output(5) 		VIO = 0.5 VPP at 1 MHz ~1 pF
RIO Insulation resistance,
input to output(5) 		VIO = 500 V at TA = 25°C > 1012 Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production test)		 5700 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.

 
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