DLPS037H
October 2014 – June 2024
DLPC900
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
5.7
Power-Up and Power-Down Timing Requirements
5.7.1
Power-Up
5.7.2
Power-Down
5.8
JTAG Interface: I/O Boundary Scan Application Timing Requirements
5.9
JTAG Interface: I/O Boundary Scan Application Switching Characteristics
5.10
Programmable Output Clocks Switching Characteristics
5.11
Port 1 and 2 Input Pixel Interface Timing Requirements
5.12
Two Pixels Per Clock (48-Bit Bus) Timing Requirements
5.13
Synchronous Serial Port (SSP) Switching Characteristics
5.14
DMD Interface Switching Characteristics
5.15
DMD LVDS Interface Switching Characteristics
5.16
Source Input Blanking Requirements
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
DMD Configurations
6.3.2
Video Timing Input Blanking Specification
6.3.3
Board-Level Test Support
6.3.4
Two Controller Considerations
6.3.5
Memory Design Considerations
6.3.5.1
Flash Memory Optimization
6.3.5.2
Operating Modes
6.3.5.3
DLPC900 External Memory Space
6.3.5.4
Minimizing Memory Space
6.3.5.5
Minimizing Board Size
6.3.5.5.1
Package Selection
6.3.5.5.2
Large Density Flash
6.3.5.5.2.1
Combining Two Chip-Selects with One 32-Megabyte Flash
6.3.5.5.2.2
Combining Three Chip-Selects with One 64-Megabyte Flash
6.3.5.5.2.3
Combining Three Chip-Selects with One 128-Megabyte Flash
6.3.5.6
Minimizing Board Space
6.3.5.7
Flash Memory
6.4
Device Functional Modes
6.4.1
Structured Light Application
7
Application and Implementation
7.1
Application Information
7.2
Typical Applications
7.2.1
Typical Two Controller Chipset
7.2.1.1
Design Requirements
7.2.1.2
Detailed Design Procedure
7.2.1.2.1
DLPC900 System Interfaces
7.2.1.2.1.1
Control Interface
7.2.1.2.1.2
Input Data Interfaces
7.2.1.2.1.3
DLPC900 System Output Interfaces
7.2.1.2.1.3.1
Illumination Interface
7.2.1.2.1.3.2
Trigger and Sync Interface
7.2.1.2.1.4
DLPC900 System Support Interfaces
7.2.1.2.1.4.1
Reference Clock and PLL
7.2.1.2.1.4.2
Program Memory Flash Interface
7.2.1.2.1.4.3
DMD Interface
7.2.2
Typical Single Controller Chipset
8
Power Supply Recommendations
8.1
System Power Regulation
8.1.1
Power Distribution System
8.1.1.1
1.15V System Power
8.1.1.2
1.8V System Power
8.1.1.3
3.3-V System Power
8.2
System Environment and Defaults
8.2.1
DLPC900 System Power-Up and Reset Default Conditions
8.3
System Power-Up Sequence
8.3.1
Power-On Sense (POSENSE) Support
8.3.2
Power Good (PWRGOOD) Support
8.3.3
5V Tolerant Support
8.4
System Reset Operation
8.4.1
Power-Up Reset Operation
8.4.2
System Reset Operation
9
Layout
9.1
Layout Guidelines
9.1.1
General PCB Recommendations
9.1.2
PCB Layout Guidelines for Internal Controller PLL Power
9.1.3
PCB Layout Guidelines for Quality Video Performance
9.1.4
Recommended MOSC Crystal Oscillator Configuration
9.1.5
Spread Spectrum Clock Generator Support
9.1.6
GPIO Interface
9.1.7
General Handling Guidelines for Unused CMOS-Type Pins
9.1.8
DMD Interface Considerations
9.1.8.1
Flex Connector Plating
9.1.9
PCB Design Standards
9.1.10
Signal Layers
9.1.11
Trace Widths and Minimum Spacing
9.1.12
Trace Impedance and Routing Priority
9.1.13
Power and Ground Planes
9.1.14
Power Vias
9.1.15
Decoupling
9.1.16
Fiducials
9.2
Layout Example
9.3
Thermal Considerations
10
Device and Documentation Support
10.1
Device Support
10.1.1
Device Nomenclature
10.1.2
Device Markings
10.1.3
DEFINITIONS—Video Timing Parameters
10.2
Documentation Support
10.2.1
Related Documentation
10.3
Receiving Notification of Documentation Updates
10.4
Support Resources
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
5.9
JTAG Interface: I/O Boundary Scan Application Switching Characteristics
Switching characteristics over recommended operating conditions, C
L
(min timing) = 5pF, C
L
(max timing) = 85pF (unless otherwise noted)
PARAMETER
FROM (INPUT)
TO (OUTPUT)
MIN
MAX
UNIT
t
pd
Output propagation, clock to Q
TCK↑
TDO1
3
12
ns
Figure 5-6
I/O Boundary Scan