DLPS133B June   2019  – July 2024 TPS99001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics—Analog to Digital Converter
    6. 5.6  Electrical Characteristics—Voltage Regulators
    7. 5.7  Electrical Characteristics—Temperature and Voltage Monitors
    8. 5.8  Electrical Characteristics—Current Consumption
    9. 5.9  Power-Up Timing Requirements
    10. 5.10 Power-Down Timing Requirements
    11. 5.11 Timing Requirements—Sequencer Clock
    12. 5.12 Timing Requirements—Host and Diagnostic Port SPI Interface
    13. 5.13 Timing Requirements—ADC Interface
    14. 5.14 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog to Digital Converter
        1. 6.3.1.1 Analog to Digital Converter Input Table
      2. 6.3.2 Power Sequencing and Monitoring
        1. 6.3.2.1 Power Monitoring
      3. 6.3.3 DMD Mirror Voltage Regulator
      4. 6.3.4 Low Dropout Regulators
      5. 6.3.5 System Monitoring Features
        1. 6.3.5.1 Windowed Watchdog Circuits
        2. 6.3.5.2 Die Temperature Monitors
        3. 6.3.5.3 External Clock Ratio Monitor
      6. 6.3.6 Communication Ports
        1. 6.3.6.1 Serial Peripheral Interface (SPI)
    4. 6.4 Device Functional Modes
      1. 6.4.1 OFF
      2. 6.4.2 STANDBY
      3. 6.4.3 POWERING_DMD
      4. 6.4.4 DISPLAY_RDY
      5. 6.4.5 PARKING
      6. 6.4.6 SHUTDOWN
    5. 6.5 Register Maps
      1. 6.5.1 System Status Registers
      2. 6.5.2 ADC Control
      3. 6.5.3 General Fault Status
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Headlight
        1. 7.2.1.1 Design Requirements
  9. 8 Power Supply Recommendations
    1. 8.1 TPS99001-Q1 Power Supply Architecture
    2. 8.2 TPS99001-Q1 Power Outputs
    3. 8.3 Power Supply Architecture
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power/High Current Signals
      2. 9.1.2 Sensitive Analog Signals
      3. 9.1.3 High-Speed Digital Signals
      4. 9.1.4 Kelvin Sensing Connections
      5. 9.1.5 Ground Separation
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.3.2.1 Power Monitoring

Main asynchronous digital logic reset (DVDD_RSTZ) – Monitor of the main power of the 3.3V power supply input to the TPS99001-Q1. This monitor output is used as an asynchronous reset for all of the digital logic inside TPS99001-Q1.

TPS99001-Q1 Internal DVDD MonitorFigure 6-2 Internal DVDD Monitor

The PROJ_ON pin is the main on/off switch for the DLP subsystem. 1 is ON, 0 is OFF. Once DVDD_ARSTZ is released, TPS99001-Q1 will begin sampling the PROJ_ON pin. If it is low, the system stays in the OFF state. If it goes high, TPS99001-Q1 begins to progress through the power-on process.

The TPS99001-Q1 includes a VMAIN brown out monitor function. A voltage monitor observes the voltage on the VMAIN input pin, as shown in Figure 6-3. The Zener may be necessary for overvoltage protection of the pin, in case the voltage being monitored has the potential to go high, such as a battery input.

Either PROJ_ON or VMAIN may be used to turn the system on and off, and doing so will remove power to the DLPC23x-Q1. For fast control of turning the display on and off without removing power to the DLPC23x-Q1, change the operating mode of the DLPC23x-Q1 embedded software between 'Standby' and 'Display'.

TPS99001-Q1 VMAIN Brown Out MonitorFigure 6-3 VMAIN Brown Out Monitor

This monitor is used to provide the DLP subsystem with an early warning that power to the unit is going away. The system will park the DMD mirrors and proceed to a ready-for-power-off state if the VMAIN input voltage falls below a fixed threshold. External resistors should be used to divide the input power rail. Once a VMAIN brownout occurs, the main power rails to the TPS99001-Q1 must remain within their operating ranges until the TPS99001-Q1 power-down is complete.

The main power rails to the chipset (6V, 3.3V, 1.8V, and 1.1V) are monitored with real-time power monitors as well. Each of these monitors is logically 'OR'ed together to produce the pwrgood2 signal in Figure 6-4.

TPS99001-Q1 Real-Time Power Rail MonitorsFigure 6-4 Real-Time Power Rail Monitors

Additionally, all power within the TPS99001-Q1 can be monitored by the ADC function. DLPC23x-Q1 software configures the ADC block to collect all voltage information in the system each frame. Any gross out of specification issues are captured and reported as system errors in the DLPC23x-Q1 system status.