DLPS133B June   2019  – July 2024 TPS99001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics—Analog to Digital Converter
    6. 5.6  Electrical Characteristics—Voltage Regulators
    7. 5.7  Electrical Characteristics—Temperature and Voltage Monitors
    8. 5.8  Electrical Characteristics—Current Consumption
    9. 5.9  Power-Up Timing Requirements
    10. 5.10 Power-Down Timing Requirements
    11. 5.11 Timing Requirements—Sequencer Clock
    12. 5.12 Timing Requirements—Host and Diagnostic Port SPI Interface
    13. 5.13 Timing Requirements—ADC Interface
    14. 5.14 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog to Digital Converter
        1. 6.3.1.1 Analog to Digital Converter Input Table
      2. 6.3.2 Power Sequencing and Monitoring
        1. 6.3.2.1 Power Monitoring
      3. 6.3.3 DMD Mirror Voltage Regulator
      4. 6.3.4 Low Dropout Regulators
      5. 6.3.5 System Monitoring Features
        1. 6.3.5.1 Windowed Watchdog Circuits
        2. 6.3.5.2 Die Temperature Monitors
        3. 6.3.5.3 External Clock Ratio Monitor
      6. 6.3.6 Communication Ports
        1. 6.3.6.1 Serial Peripheral Interface (SPI)
    4. 6.4 Device Functional Modes
      1. 6.4.1 OFF
      2. 6.4.2 STANDBY
      3. 6.4.3 POWERING_DMD
      4. 6.4.4 DISPLAY_RDY
      5. 6.4.5 PARKING
      6. 6.4.6 SHUTDOWN
    5. 6.5 Register Maps
      1. 6.5.1 System Status Registers
      2. 6.5.2 ADC Control
      3. 6.5.3 General Fault Status
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Headlight
        1. 7.2.1.1 Design Requirements
  9. 8 Power Supply Recommendations
    1. 8.1 TPS99001-Q1 Power Supply Architecture
    2. 8.2 TPS99001-Q1 Power Outputs
    3. 8.3 Power Supply Architecture
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power/High Current Signals
      2. 9.1.2 Sensitive Analog Signals
      3. 9.1.3 High-Speed Digital Signals
      4. 9.1.4 Kelvin Sensing Connections
      5. 9.1.5 Ground Separation
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.3.1.1 Analog to Digital Converter Input Table

Table 6-1 Analog to Digital Converter Input Table
PARAMETERINTERNAL OR EXTERNALTEST CONDITIONS(1)MINTYPMAXUNIT
Channel 0, GainLow side sense ampExternalGain set to 24x22.562425.44V/V
Channel 0, GainLow side sense ampExternalGain set to 12x11.281212.72V/V
Channel 0, GainLow side sense ampExternalGain set to 9x8.4699.54V/V
Channel 1, GainADC_IN1_PAD (LED_ANODE)External0.9801.0001.020V/V
Channel 2, GainADC_IN2_PAD (VLED)External0.9801.0001.020V/V
Channel 3, GainADC_IN3_PADExternal0.9801.0001.020V/V
Channel 4, GainADC_IN4_PADExternal0.9801.0001.020V/V
Channel 5, GainADC_IN5_PAD (R_LED_THERM)External0.9801.0001.020V/V
Channel 6, GainADC_IN6_PAD (G_LED_THERM)External0.9801.0001.020V/V
Channel 7, GainADC_IN7_PAD (B_LED_THERM)External0.9801.0001.020V/V
Channel 8, GainVBIASInternal0.05960.06210.0646V/V
Channel 9, GainVOFFSETInternal0.11120.1170.1218V/V
Channel 10, GainVRESETInternal–0.1978–0.190–0.1822V/V
Channel 10, OffsetVRESETInternal–1.217–1.1935–1.169V
Channel 11, GainVMAINInternal0.525460.5590.59254V/V
Channel 12, GainDVDDInternal0.313020.3330.35298V/V
Channel 13, GainV1.1Internal0.657060.6990.74094V/V
Channel 14, GainV1.8Internal0.403260.4290.45474V/V
Channel 15, GainV3.3Internal0.22090.2350.2491V/V
Channel 17, Gainext ADC VREFInternal0.490.50.51V/V
Channel 18, GainDriver PowerInternal0.203980.2170.23002V/V
Channel 19, GainDie Temp1Internal0.4900.5000.510V/V
Channel 20, GainDie Temp2Internal0.4900.5000.510V/V
Channel 28, Gain Channel not usedInternal
Channel 29, GainMain Bandgap, 0.5VInternal0.9801.0001.020V/V
(1) The conversionformula is (X + Offset) × Gain. X is the input voltage. Offset is 0V unless specified above.