DLPS230C December   2022  – August 2024 DLP4620S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
      1. 5.4.1 Illumination Overfill Diagram
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
      1.      Electrical and Timing Diagrams
    8. 5.8  Switching Characteristics
      1. 5.8.1 LPSDR and Test Load Circuit Diagrams
    9. 5.9  System Mounting Interface Loads
      1.      System Interface Loads Diagram
    10. 5.10 Micromirror Array Physical Characteristics
      1. 5.10.1 Micromirror Array Physical Characteristics Diagram
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 SubLVDS Data Interface
      2. 6.3.2 Low Speed Interface for Control
      3. 6.3.3 DMD Voltage Supplies
      4. 6.3.4 Asynchronous Reset
      5. 6.3.5 Temperature Sensing Diode
        1. 6.3.5.1 Temperature Sense Diode Theory
    4. 6.4 System Optical Considerations
      1. 6.4.1 Numerical Aperture and Stray Light Control
      2. 6.4.2 Pupil Match
      3. 6.4.3 Illumination Overfill
    5. 6.5 DMD Image Performance Specification
    6. 6.6 Micromirror Array Temperature Calculation
      1. 6.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
    7. 6.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application Overview
      2. 7.2.2 Input Image Resolution
      3. 7.2.3 Reference Design
      4. 7.2.4 Application Mission Profile Consideration
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply Power-Up Procedure
      2. 7.3.2 Power Supply Power-Down Procedure
      3. 7.3.3 Power Supply Sequencing Requirements
    4. 7.4 Layout Guidelines
    5. 7.5 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Device Markings
    2. 8.2 Third-Party Products Disclaimer
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 DMD Handling
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

3 Description

The DLP® DLP4620S-Q1 automotive digital micromirror device (DMD), combined with the DLPC231S-Q1 DMD controller and TPS99000S-Q1 system management and illumination controller, provides the capability to achieve high-performance, high-resolution augmented reality head-up display (HUD). The 2:1 aspect ratio supports very wide aspect ratio designs, and the 0.9MP resolution enables retinal limited displays to be achieved in HUD applications. The DLP4620S-Q1 has a good balance of optical throughput and resolution enabling a wide field of view and a large driver eye box for enhanced user experience. This chipset, coupled with LEDs or lasers and an optical system, enables deep saturated colors of 125% NTSC, extremely high brightness of more than 15,000cd/m2, high dynamic dimming ratio of more than 5000:1, and high solar load tolerance. The DLP4620S-Q1 automotive DMD micromirror array is configured for bottom illumination, which enables highly efficient and more compact optical engine designs to support left and right driver configurations. The DLP4620S-Q1 device is available in a panel package for optimized system cost. The package has low thermal resistance to the DMD array to enable efficient thermal solutions.

Device Information
PART NUMBERPACKAGE(1)PACKAGE SIZE
DLP4620S-Q1

FQX

25.2mm × 11.0mm
(1) For more information, see the Mechanical, Packaging, and Orderable sections.
DLP4620S-Q1 DLP4620S-Q1 Chipset System Block DiagramDLP4620S-Q1 Chipset System Block Diagram