During power-up, VDD
must always start and settle before VOFFSET plus tDELAY1
specified in Table 8-1, VBIAS, and VRESET voltages are applied to the
DMD.
During power-up, it is a strict requirement that
the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in the recommended operating conditions.
During power-up, there is no
requirement for the relative timing of VRESET with respect to
VBIAS.
Power supply slew rates during power-up are
flexible, provided that the transient voltage levels follow the requirements
specified in the absolute maximum ratings, in the recommended operating
conditions, and in Table 8-1.
During power-up, LVCMOS input pins must not be
driven high until after VDD has settled at operating voltage listed
in the recommended operating conditions.