DLPU018J October   2014  – June 2024 DLPC900

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documents from Texas Instruments
    3.     If You Need Assistance
    4.     Trademarks
  3. 1Interface Protocol
    1. 1.1 I2C Interface
      1. 1.1.1 I2C Transaction Structure
        1. 1.1.1.1 I2C START Condition
        2. 1.1.1.2 I2C STOP Condition
        3. 1.1.1.3 DLPC900 I2C Secondary Controller Address 
        4. 1.1.1.4 DLPC900 I2C Sub-Address and Data Bytes
      2. 1.1.2 Example I2C Read Command Sequence
        1. 1.1.2.1 I2C Read Command Example with Parameters
      3. 1.1.3 Example I2C Write Command Sequence
    2. 1.2 USB Interface
      1. 1.2.1 USB Transaction Sequence
      2. 1.2.2 USB Read Transaction Sequence Example
      3. 1.2.3 USB Write Transaction Sequence Example
    3. 1.3 INIT_DONE Signal
  4. 2DLPC900 Control Commands
    1. 2.1 DLPC900 Status Commands
      1. 2.1.1 Hardware Status
      2. 2.1.2 System Status
      3. 2.1.3 Main Status
      4. 2.1.4 Retrieve Firmware Version
      5. 2.1.5 Reading Hardware Configuration and Firmware Tag Information
      6. 2.1.6 Read Error Code
      7. 2.1.7 Read Error Description
    2. 2.2 DLPC900 Firmware Programming Commands
      1. 2.2.1  Read Status
      2. 2.2.2  Enter Program Mode
      3. 2.2.3  Exit Program Mode
      4. 2.2.4  Read Control
      5. 2.2.5  Start Address
      6. 2.2.6  Erase Sector
      7. 2.2.7  Download Flash Data Size
      8. 2.2.8  Download Data
      9. 2.2.9  Calculate Checksum
      10. 2.2.10 Controller Enable/Disable Command
    3. 2.3 Chipset Control Commands
      1. 2.3.1  Chipset Configuration Commands
        1. 2.3.1.1 Power Mode
        2. 2.3.1.2 DMD Standby and Idle Modes
        3. 2.3.1.3 DMD Park/Unpark (No Longer Recommended)
        4. 2.3.1.4 Curtain Color
      2. 2.3.2  Parallel Interface Configuration
        1. 2.3.2.1 Parallel Port Configuration
        2. 2.3.2.2 Input Data Channel Swap
      3. 2.3.3  Input Source Commands
        1. 2.3.3.1 Port and Clock Configuration
        2. 2.3.3.2 Input Source Configuration
        3. 2.3.3.3 Input Pixel Data Format
        4. 2.3.3.4 Internal Test Pattern Select
        5. 2.3.3.5 Internal Test Patterns Color
        6. 2.3.3.6 Load Image
      4. 2.3.4  Image Flip
        1. 2.3.4.1 Long-Axis Image Flip
        2. 2.3.4.2 Short Axis Image Flip
      5. 2.3.5  IT6535 Power Mode
      6. 2.3.6  Gamma Configuration and Enable
      7. 2.3.7  LED Driver Commands
        1. 2.3.7.1 LED Enable Outputs
          1. 2.3.7.1.1 LED PWM Polarity
        2. 2.3.7.2 LED Driver Current
        3. 2.3.7.3 Minimum LED Pulse Width in microseconds (µs)
        4. 2.3.7.4 Minimum LED Pulse Width in nanoseconds (ns)
        5. 2.3.7.5 Get Minimum LED Pattern Exposure in microseconds (µs)
        6. 2.3.7.6 Get Minimum LED Pattern Exposure in nanoseconds (ns)
      8. 2.3.8  GPIO Commands
        1. 2.3.8.1 GPIO Configuration
        2. 2.3.8.2 GPIO Clock Configuration
        3. 2.3.8.3 GPIO Busy
      9. 2.3.9  Pulse Width Modulated (PWM) Control
        1. 2.3.9.1 PWM Setup
        2. 2.3.9.2 PWM Enable
      10. 2.3.10 Batch File Commands
        1. 2.3.10.1 Batch File Name
        2. 2.3.10.2 Batch File Execute
        3. 2.3.10.3 Batch File Delay
        4. 2.3.10.4 Batch File Example
    4. 2.4 Display Mode Commands
      1. 2.4.1 Display Mode Selection
        1. 2.4.1.1 Video Mode Resolution
        2. 2.4.1.2 Input Display Resolution
        3. 2.4.1.3 DMD Block Load
        4. 2.4.1.4 Minimum Exposure Times
      2. 2.4.2 Image Header
      3. 2.4.3 Pattern Image Compression
        1. 2.4.3.1 Run-Length Encoding
          1. 2.4.3.1.1 RLE Compression Example
        2. 2.4.3.2 Enhanced Run-Length Encoding
          1. 2.4.3.2.1 Enhanced RLE Compression Example
          2. 2.4.3.2.2 End of Image Padding
      4. 2.4.4 Pattern Display Commands
        1. 2.4.4.1 Trigger Commands
          1. 2.4.4.1.1 Trigger Out 1
          2. 2.4.4.1.2 Trigger Out 2
          3. 2.4.4.1.3 Trigger In 1
          4. 2.4.4.1.4 Trigger In 2
        2. 2.4.4.2 LED Enable Delay Commands
          1. 2.4.4.2.1 Red LED Enable Delay
          2. 2.4.4.2.2 Green LED Enable Delay
          3. 2.4.4.2.3 Blue LED Enable Delay
        3. 2.4.4.3 Pattern Display Commands
          1. 2.4.4.3.1 Pattern Display Start/Stop
          2. 2.4.4.3.2 Pattern Display Invert Data
          3. 2.4.4.3.3 Pattern Display LUT Configuration
          4. 2.4.4.3.4 Pattern Display LUT Reorder Configuration
          5. 2.4.4.3.5 Pattern Display LUT Definition
        4. 2.4.4.4 Pattern On-The-Fly Commands
          1. 2.4.4.4.1 Initialize Pattern BMP Load
          2. 2.4.4.4.2 Pattern BMP Load
        5. 2.4.4.5 I2C Pass Through Commands
          1. 2.4.4.5.1 I2C Pass Through Configuration
          2. 2.4.4.5.2 I2C Pass Through Write
          3. 2.4.4.5.3 I2C Pass Through Read
    5. 2.5 Debug Mode Commands
      1. 2.5.1 Destination Controller Command (Dual Controller System)
      2. 2.5.2 Memory Read/Write Command
        1. 2.5.2.1 Valid Memory Address Ranges
      3. 2.5.3 Debug Mask Command
  5. 3DLPC900 Fault Status
    1. 3.1 DLPC900 FAULT_STATUS Locations
    2. 3.2 DLPC900 FAULT_STATUS Interpretation
  6. 4Power-Up and Power-Down and Initialization Considerations
    1. 4.1 Power-Up
    2. 4.2 Power-Down
    3. 4.3 Power-Up Auto-Initialization
  7. 5Command Examples
    1. 5.1 Video Pattern Mode Example
    2. 5.2 Pre-Stored Pattern Mode Example
    3. 5.3 Pattern On-The-Fly Example
    4. 5.4 I2C Pass Through Write Example
    5. 5.5 I2C Pass Through Read Example
  8.   A Register Quick Reference
    1.     A.1 I2C Register Quick Reference
    2.     A.2 Command Guide
  9.   B Batch File Command Descriptors
    1.     B.1 Command Descriptors
  10.   C Revision History

2.4 Display Mode Commands

The DLPC900 display consists of several parameters which dictate the loading of the DMD and the control of PWM to the LEDs. The DLPC900 supports four main display modes:

  • Video Mode
  • Video Pattern Mode
  • Pre-Stored Pattern Mode
  • Pattern On-The-Fly Mode

The Display Mode Selection command (Section 2.4.1) selects between these modes.

In Video mode, the DLPC900 30-bit RGB interface supports up to the native resolution of the attached DMD. The DLPC900 processes the digital input image and converts the data into the appropriate format.

The DLPC900 offers scaling and cropping functions to appropriately display resolutions on single controller DMDs.

The DLPC900 combined with dual controller DMDs does not support scaling or cropping functions.

In the latter three modes, the DLPC900 provides high-speed pattern rates. These modes support only 24-bit data input through the DLPC900 RGB interface (Video Pattern Mode), from flash memory (Pre-Stored Pattern Mode), or dynamically loaded (Pattern On-The-Fly Mode). These modes are well-suited for techniques such as structured light, additive manufacturing, or digital exposure. The DLPC900 also has the capability to display a set of patterns and signal a camera to capture when these patterns are displayed.

Figure 2-4 shows the DLPC900 Single Controller DMD block diagram and Figure 2-5 shows the DLPC900 Dual Controller DMD block diagram. The main functional blocks for the four display modes are shown in these diagrams.

Note: For TI components in these diagrams, please refer to the latest DLPLCRC900EVM Single DLPC900 Design Files and DLPLCRC900DEVM Dual DLPC900 Design Files for current TI part numbers.

DLPC900 DLPC900 Single Controller System Block Diagram Figure 2-4 DLPC900 Single Controller System Block Diagram
DLPC900 DLPC900 Dual Controller System Block Diagram Figure 2-5 DLPC900 Dual Controller System Block Diagram

In Video mode, the DLPC900 operates on a per-frame basis where it takes the input data and appropriately allocates it in a frame. For example, a 24-bit RGB input image is allocated into a 60-Hz frame by dividing each color (red, green, and blue) into specific percentages of the frame. Therefore, for a 40% red, 45% green, and 15% blue ratio, results in the red, green, and blue colors having a 6.67-, 7.5-, and 2.54-ms time slot allocated, respectively. Because each color has an 8-bit depth, each color time slot is further divided into bit-planes, as shown in Figure 2-6. A bit-plane is the two-dimensional arrangement of one bit extracted from all the pixels in the full color 2D image.

DLPC900 Bit-Planes of a 24-Bit RGB Image Figure 2-6 Bit-Planes of a 24-Bit RGB Image

The length of each bit-plane in the time slot is weighted by the corresponding power of two of its binary representation resulting in a binary pulse-width modulation of the image. For example, a 24-bit RGB input has three colors with 8-bit depth each. Each color time slot is divided into eight bit-planes, with the sum of the weight of all bit planes in the time slot equal to 255. See Figure 2-7 for an illustration of this partition of the bits in a frame.

DLPC900 Bit Partition in a Frame for an 8-Bit Monochrome Image Figure 2-7 Bit Partition in a Frame for an 8-Bit Monochrome Image

Therefore, a single video frame is composed of a series of bit-planes. Because the DMD mirrors can be either on or off, an image is created by turning on the mirrors corresponding to the bit set in a bit-plane. With binary pulse width modulation, the intensity level of the color is reproduced by controlling the amount of time the mirror is on. For a 24-bit RGB frame image inputted to the DLPC900 controller, the DLPC900 controller creates 24 bit-planes, stores them in internal embedded DRAM, and sends them to the DMD, one bitplane at a time. The bit weight controls the illumination intensity of the bit-plane where smaller the bit weight is the less intense the bit-plane becomes. To improve image quality in video frames, these bit-planes, time slots, and color frames are shuffled and interleaved within the pixel processing functions of the DLPC900 controller.

For other applications where one-to-one pixel mapping to the DMD micromirror is required, the scaling, cropping, and pixel processing functions are disabled and a specific set of patterns is used. The bit-depth of the pattern is then allocated into the corresponding binary weighted time slots. Furthermore, output trigger signals are also synchronized with these time slots to indicate when the image is displayed. For structured light applications, this mechanism provides the capability to display a set of patterns and signal a camera to capture these patterns overlaid on an object.