DLPU041G April 2016 – July 2024 DLPC230-Q1 , DLPC230S-Q1
The main application commands the DMD into a testing mode and the DMD writes known values into the memory cells below its pixels. The DMD then reads back the state of each memory cell and drives a signal to the DLPC230-Q1 to indicate pass or fail for each column of the DMD memory. A column is a top-to-bottom, width 1 array of memory cells (referred to as a DMD row by DMD design convention). A column will be reported as a fail if one or more memory cells in that column reads an incorrect value. The DLPC230-Q1 main application then sums the number of failed columns. Note that results cannot be reported at a per-memory-cell level of detail because the results are only transmitted to the DLPC230-Q1 at column-level granularity.
This process is executed four times and the number of failed columns are summed from each execution. The four executions includes two opposite checkerboard patterns on the two halves of the DMD. The use of two checkerboard patterns ensures that every memory cell is tested at both high and low state. Although the results of these four tests are summed, the data from each test is unique meaning that no memory cell fail should be counted more than once.
The pass/fail criteria are shown in Table 6-40.
| NUMBER OF COLUMN FAILS | TEST RESULT |
|---|---|
| 0 or 1 | Pass |
| 2 or more | Fail |