DLPU041G April   2016  – July 2024 DLPC230-Q1 , DLPC230S-Q1

 

  1.   1
  2.   Trademarks
  3. 1 Introduction
    1. 1.1 Document Overview
    2. 1.2 Software Overview
    3. 1.3 Head-Up Display Overview
  4. 2 Electrical Interface
    1. 2.1 Power-Up Signals
      1. 2.1.1 STAY-IN-BOOT (TSTPT_0)
      2. 2.1.2 HOST_IF_SEL
      3. 2.1.3 CRCZ_CHKSUM_SEL
      4. 2.1.4 HOST_SPI_MODE
        1. 2.1.4.1 Boot Flow Debug
      5. 2.1.5 SPREAD-SPECTRUM-DISABLE (TSTPT_5)
    2. 2.2 System Signals
      1. 2.2.1 HOST_IRQ
      2. 2.2.2 GPIO
  5. 3 Communication Protocol
    1. 3.1 Command Protocol
    2. 3.2 SPI Specifications
    3. 3.3 I2C Specifications
    4. 3.4 Write
      1. 3.4.1 Short Write
        1. 3.4.1.1 SPI Short Write
        2. 3.4.1.2 I2C Short Write
      2. 3.4.2 Bulk Write
        1. 3.4.2.1 SPI Bulk Write
        2. 3.4.2.2 I2C Bulk Write
      3. 3.4.3 Write Command Handling
    5. 3.5 Read
      1. 3.5.1 Read Pre-Fetch
        1. 3.5.1.1 SPI Read Pre-Fetch
        2. 3.5.1.2 I2C Read Pre-Fetch
      2. 3.5.2 Read Activate
        1. 3.5.2.1 SPI Read Activate
        2. 3.5.2.2 I2C Read Activate
      3. 3.5.3 Short Status Read
        1. 3.5.3.1 SPI Short Status Read
        2. 3.5.3.2 I2C Short Status Read
      4. 3.5.4 Read Command Handling
    6. 3.6 CRC and Checksum
      1. 3.6.1 CRC Calculation
        1. 3.6.1.1 CRC Example Implementation
        2. 3.6.1.2 CRC Example
      2. 3.6.2 Checksum Calculation
    7. 3.7 Command Tags
  6. 4 System Operation
    1. 4.1 Operating Modes
      1. 4.1.1 Standby
      2. 4.1.2 Display
      3. 4.1.3 Calibration
    2. 4.2 Software Startup Procedure
  7. 5 Application and Use-Cases
    1. 5.1 Display and Source
      1. 5.1.1 Displaying an Image
      2. 5.1.2 Supported Image Processing
      3. 5.1.3 External Video
      4. 5.1.4 Test Pattern
      5. 5.1.5 Splash Image
      6. 5.1.6 Bezel Adjustment
      7. 5.1.7 Image Flip
    2. 5.2 Batch Command Sets
    3. 5.3 Flash Programming
      1. 5.3.1 Flash Program - Main Application
      2. 5.3.2 Flash Read - Main Application
      3. 5.3.3 Flash Program - Boot Application
    4. 5.4 Temperature Management
      1. 5.4.1 Temperature Management for DMD Park/Unpark
      2. 5.4.2 PWM Temperature Management Function
      3. 5.4.3 Dimming Level Override Temperature Management
    5. 5.5 ADC Measurements
      1. 5.5.1 Sequence-Aligned ADC Measurements
      2. 5.5.2 Single ADC Measurements
  8. 6 Tests and Diagnostics
    1. 6.1 Overview
    2. 6.2 Emergency Shutdown
      1. 6.2.1 Emergency Shutdown Causes
    3. 6.3 Diagnostic Memory Interface
    4. 6.4 Test Descriptions
      1. 6.4.1 Periodic Tests
        1. 6.4.1.1  Video Source Loss Detection
          1. 6.4.1.1.1 Configuration
          2. 6.4.1.1.2 Execution
          3. 6.4.1.1.3 Failure Actions
          4. 6.4.1.1.4 Error Codes
        2. 6.4.1.2  Video Tell-Tale Checksum
          1. 6.4.1.2.1 Configuration
          2. 6.4.1.2.2 Execution
          3. 6.4.1.2.3 Failure Actions
          4. 6.4.1.2.4 Error Codes
        3. 6.4.1.3  Video Frame Counter Checksum
          1. 6.4.1.3.1 One-Pixel Frame Counter
          2. 6.4.1.3.2 Seven-Pixel Frame Counter
          3. 6.4.1.3.3 Configuration
          4. 6.4.1.3.4 Execution
          5. 6.4.1.3.5 Failure Actions
          6. 6.4.1.3.6 Error Codes
        4. 6.4.1.4  Average Picture Level
          1. 6.4.1.4.1 Configuration
          2. 6.4.1.4.2 Execution
          3. 6.4.1.4.3 Failure Actions
          4. 6.4.1.4.4 Error Codes
        5. 6.4.1.5  Loss of Dimming Command
          1. 6.4.1.5.1 Configuration
          2. 6.4.1.5.2 Execution
          3. 6.4.1.5.3 Failure Actions
          4. 6.4.1.5.4 Error Codes
        6. 6.4.1.6  TPS99000-Q1 Excessive Brightness Monitor
          1. 6.4.1.6.1 Configuration
          2. 6.4.1.6.2 Execution
          3. 6.4.1.6.3 Failure Actions
          4. 6.4.1.6.4 Error Codes
        7. 6.4.1.7  Photo Feedback Monitor
          1. 6.4.1.7.1 Configuration
          2. 6.4.1.7.2 Execution
          3. 6.4.1.7.3 Failure Actions
          4. 6.4.1.7.4 Error Codes
        8. 6.4.1.8  DLPC230-Q1 Processor Memory ECC
          1. 6.4.1.8.1 Configuration
          2. 6.4.1.8.2 Execution
          3. 6.4.1.8.3 Failure Actions
          4. 6.4.1.8.4 Error Codes
        9. 6.4.1.9  Flash Table Transport CRC
          1. 6.4.1.9.1 Configuration
          2. 6.4.1.9.2 Execution
          3. 6.4.1.9.3 Failure Actions
          4. 6.4.1.9.4 Error Codes
        10. 6.4.1.10 Frame Buffer Swap Watchdog
          1. 6.4.1.10.1 Configuration
          2. 6.4.1.10.2 Execution
          3. 6.4.1.10.3 Failure Actions
          4. 6.4.1.10.4 Error Codes
        11. 6.4.1.11 Sequencer Instruction Read Watchdog
          1. 6.4.1.11.1 Configuration
          2. 6.4.1.11.2 Execution
          3. 6.4.1.11.3 Failure Actions
          4. 6.4.1.11.4 Error Codes
        12. 6.4.1.12 DMD Reset Instruction Watchdog
          1. 6.4.1.12.1 Configuration
          2. 6.4.1.12.2 Execution
          3. 6.4.1.12.3 Failure Actions
          4. 6.4.1.12.4 Error Codes
        13. 6.4.1.13 DLPC230-Q1 System Voltage Monitor
          1. 6.4.1.13.1 Configuration
          2. 6.4.1.13.2 Execution
          3. 6.4.1.13.3 Failure Actions
          4. 6.4.1.13.4 Error Codes
        14. 6.4.1.14 DLPC230-Q1 DMD Voltage Monitor
          1. 6.4.1.14.1 Configuration
          2. 6.4.1.14.2 Execution
          3. 6.4.1.14.3 Failure Actions
          4. 6.4.1.14.4 Error Codes
        15. 6.4.1.15 DLPC230-Q1 TPS99000-Q1 Bandgap Monitor
          1. 6.4.1.15.1 Configuration
          2. 6.4.1.15.2 Execution
          3. 6.4.1.15.3 Failure Actions
          4. 6.4.1.15.4 Error Codes
        16. 6.4.1.16 DMD Temperature Monitor
          1. 6.4.1.16.1 Configuration
          2. 6.4.1.16.2 Execution
          3. 6.4.1.16.3 Failure Actions
          4. 6.4.1.16.4 Error Codes
        17. 6.4.1.17 DMD Clock Monitor
          1. 6.4.1.17.1 Configuration
          2. 6.4.1.17.2 Execution
          3. 6.4.1.17.3 Failure Actions
          4. 6.4.1.17.4 Error Codes
        18. 6.4.1.18 DMD High Speed Interface Training
          1. 6.4.1.18.1 Configuration
          2. 6.4.1.18.2 Execution
          3. 6.4.1.18.3 Failure Actions
          4. 6.4.1.18.4 Error Codes
        19. 6.4.1.19 DMD Low Speed Interface Test
          1. 6.4.1.19.1 Configuration
          2. 6.4.1.19.2 Execution
          3. 6.4.1.19.3 Failure Actions
          4. 6.4.1.19.4 Error Codes
        20. 6.4.1.20 TPS99000-Q1 DLPC230-Q1 Processor Watchdog (WD1)
          1. 6.4.1.20.1 Configuration
          2. 6.4.1.20.2 Execution
          3. 6.4.1.20.3 Failure Actions
          4. 6.4.1.20.4 Error Codes
        21. 6.4.1.21 TPS99000-Q1 DLPC230-Q1 Sequencer Watchdog (WD2)
          1. 6.4.1.21.1 Configuration
          2. 6.4.1.21.2 Execution
          3. 6.4.1.21.3 Failure Actions
          4. 6.4.1.21.4 Error Codes
        22. 6.4.1.22 TPS99000-Q1 Temperature Warning / Error
          1. 6.4.1.22.1 Configuration
          2. 6.4.1.22.2 Execution
          3. 6.4.1.22.3 Failure Actions
          4. 6.4.1.22.4 Error Codes
        23. 6.4.1.23 TPS99000-Q1 Clock Ratio Monitor
          1. 6.4.1.23.1 Configuration
          2. 6.4.1.23.2 Execution
          3. 6.4.1.23.3 Failure Actions
          4. 6.4.1.23.4 Error Codes
        24. 6.4.1.24 TPS99000-Q1 Register Password Lock
          1. 6.4.1.24.1 Configuration
          2. 6.4.1.24.2 Execution
          3. 6.4.1.24.3 Failure Actions
          4. 6.4.1.24.4 Error Codes
        25. 6.4.1.25 TPS99000-Q1 Register Checksum
          1. 6.4.1.25.1 Configuration
          2. 6.4.1.25.2 Execution
          3. 6.4.1.25.3 Failure Actions
          4. 6.4.1.25.4 Error Codes
        26. 6.4.1.26 Software Monitor Thread
          1. 6.4.1.26.1 Configuration
          2. 6.4.1.26.2 Execution
          3. 6.4.1.26.3 Failure Actions
          4. 6.4.1.26.4 Error Codes
      2. 6.4.2 Non-Periodic Tests
        1. 6.4.2.1  Execution Time
        2. 6.4.2.2  DLPC230-Q1 Front End Functional BIST (Main)
          1. 6.4.2.2.1 Configuration
          2. 6.4.2.2.2 Execution
          3. 6.4.2.2.3 Failure Actions
          4. 6.4.2.2.4 Error Codes
        3. 6.4.2.3  DLPC230-Q1 Back End Functional BIST (Main)
          1. 6.4.2.3.1 Configuration
          2. 6.4.2.3.2 Execution
          3. 6.4.2.3.3 Failure Actions
          4. 6.4.2.3.4 Error Codes
        4. 6.4.2.4  DLPC230-Q1 Memory BISTs (Main)
          1. 6.4.2.4.1 Configuration
          2. 6.4.2.4.2 Execution
          3. 6.4.2.4.3 Failure Actions
          4. 6.4.2.4.4 Error Codes
        5. 6.4.2.5  TPS99000-Q1 Interface Signal Connection Test (Main)
          1. 6.4.2.5.1 Configuration
          2. 6.4.2.5.2 Execution
          3. 6.4.2.5.3 Failure Actions
          4. 6.4.2.5.4 Error Codes
        6. 6.4.2.6  DAC to ADC Loop BIST (Main)
          1. 6.4.2.6.1 Configuration
          2. 6.4.2.6.2 Execution
          3. 6.4.2.6.3 Failure Actions
          4. 6.4.2.6.4 Error Codes
        7. 6.4.2.7  DMD Memory Test (Main)
          1. 6.4.2.7.1 Configuration
          2. 6.4.2.7.2 Execution
          3. 6.4.2.7.3 Failure Actions
          4. 6.4.2.7.4 Error Codes
        8. 6.4.2.8  Flash Data Verification (Boot/Main)
          1. 6.4.2.8.1 Configuration
          2. 6.4.2.8.2 Execution
          3. 6.4.2.8.3 Failure Actions
          4. 6.4.2.8.4 Error Codes
        9. 6.4.2.9  DLPC230-Q1 Boot ROM CRC (Boot)
          1. 6.4.2.9.1 Configuration
          2. 6.4.2.9.2 Execution
          3. 6.4.2.9.3 Failure Actions
          4. 6.4.2.9.4 Error Codes
        10. 6.4.2.10 DLPC230-Q1 Flash Table CRC (Boot)
          1. 6.4.2.10.1 Configuration
          2. 6.4.2.10.2 Execution
          3. 6.4.2.10.3 Failure Actions
          4. 6.4.2.10.4 Error Codes
        11. 6.4.2.11 DLPC230-Q1 Main Application CRC (Boot)
          1. 6.4.2.11.1 Configuration
          2. 6.4.2.11.2 Execution
          3. 6.4.2.11.3 Failure Actions
          4. 6.4.2.11.4 Error Codes
        12. 6.4.2.12 DLPC230-Q1 Command and Flash Interface Memory Test (Boot)
          1. 6.4.2.12.1 Configuration
          2. 6.4.2.12.2 Execution
          3. 6.4.2.12.3 Failure Actions
          4. 6.4.2.12.4 Error Codes
      3. 6.4.3 Interface Tests
        1. 6.4.3.1 Temperature Sensor Interface
          1. 6.4.3.1.1 Failure Actions
        2. 6.4.3.2 DLPC230-Q1 to TPS99000-Q1 SPI Interface
          1. 6.4.3.2.1 Failure Actions
        3. 6.4.3.3 DLPC230-Q1 to TPS99000-Q1 ADC Interface
          1. 6.4.3.3.1 Failure Actions
        4. 6.4.3.4 DMD Socket Connectivity Test
          1. 6.4.3.4.1 Configuration
          2. 6.4.3.4.2 Execution
          3. 6.4.3.4.3 Failure Actions
          4. 6.4.3.4.4 Error Codes
  9. 7 Commands - Boot Application
    1. 7.1 Command Table
    2. 7.2 Command Definitions
      1. 7.2.1  System Reset - Write (00h)
      2. 7.2.2  Read Pre-Fetch - Write (01h)
      3. 7.2.3  Read Activate (02h)
      4. 7.2.4  System Software Version - Read (B0h)
      5. 7.2.5  Flash Device ID - Read (B1h)
      6. 7.2.6  Short Status - Read (C0h)
      7. 7.2.7  Error History - Read (C1h)
      8. 7.2.8  Clear Short Status Errors - Write (C2h)
      9. 7.2.9  Clear Error History - Write (C3h)
      10. 7.2.10 Flash Full Erase - Write (E0h)
      11. 7.2.11 Flash Write Data - Write (E1h)
      12. 7.2.12 Flash Verify Data - Write (E2h)
      13. 7.2.13 Flash Interface Rate - Write (E3h)
      14. 7.2.14 Flash Interface Rate - Read (E4h)
  10. 8 Commands - Main Application
    1. 8.1 Mode Availability
    2. 8.2 Command Definitions
      1. 8.2.1   System Reset - Write (00h)
      2. 8.2.2   Read Pre-Fetch - Write (01h)
      3. 8.2.3   Read Activate (02h)
      4. 8.2.4   Operating Mode - Write (03h)
      5. 8.2.5   Operating Mode - Read (04h)
      6. 8.2.6   Source Select - Write (05h)
      7. 8.2.7   Source Select - Read (06h)
      8. 8.2.8   Prepare for Source Change - Write (07h)
      9. 8.2.9   Display Image Orientation - Write (18h)
      10. 8.2.10  Display Image Orientation - Read (19h)
      11. 8.2.11  System Mode Select - Write (1Ch)
      12. 8.2.12  System Mode Select - Read (1Dh)
      13. 8.2.13  Bezel Adjustment - Write (1Fh)
      14. 8.2.14  Bezel Adjustment - Read (20h)
      15. 8.2.15  Execute Batch Command Set - Write (21h)
      16. 8.2.16  Execution Delay - Write (22h)
      17. 8.2.17  GPIO Configure - Write (23h)
      18. 8.2.18  GPIO Configure - Read (24h)
      19. 8.2.19  GPIO Outputs - Write (25h)
      20. 8.2.20  GPIO Outputs - Read (26h)
      21. 8.2.21  GPIO Reserved - Read (27h)
      22. 8.2.22  Execute Non-Periodic BIST - Write (28h)
      23. 8.2.23  External Video Checksum Control - Write (29h)
      24. 8.2.24  External Video Checksum Control - Read (2Ah)
      25. 8.2.25  External Video Checksum Settings - Write (2Bh)
      26. 8.2.26  External Video Checksum Settings - Read (2Ch)
      27. 8.2.27  DMD Socket Connectivity Test - Write (2Dh)
      28. 8.2.28  DMD Socket Connectivity Test - Read (2Eh)
      29. 8.2.29  Average Picture Level Control - Write (2Fh)
      30. 8.2.30  Average Picture Level Control - Read (30h)
      31. 8.2.31  Loss Of Dimming Control - Write (33h)
      32. 8.2.32  Loss Of Dimming Control - Read (34h)
      33. 8.2.33  PWM Temperature Management Enable - Write (35h)
      34. 8.2.34  PWM Temperature Management Enable - Read (36h)
      35. 8.2.35  PWM Temperature Management Source - Write (37h)
      36. 8.2.36  PWM Temperature Management Source - Read (38h)
      37. 8.2.37  PWM Temperature Management Duty Cycle - Read (39h)
      38. 8.2.38  Dimming Level Override Temperature Management Enable - Write (40h)
      39. 8.2.39  Dimming Level Override Temperature Management Enable - Read (41h)
      40. 8.2.40  Dimming Level Override Temperature Management Source - Write (42h)
      41. 8.2.41  Dimming Level Override Temperature Management Source - Read (43h)
      42. 8.2.42  Dimming Level OverrideTemperature Management Duty Cycle- Read (44h)
      43. 8.2.43  Dimming Level - Write (50h)
      44. 8.2.44  Dimming Level - Read (51h)
      45. 8.2.45  Contrast - Write (52h)
      46. 8.2.46  Contrast - Read (53h)
      47. 8.2.47  De-gamma Select - Write (54h)
      48. 8.2.48  De-gamma Select - Read (55h)
      49. 8.2.49  Dimming Compensation Temp Source Select - Write (58h)
      50. 8.2.50  Dimming Compensation Temp Source Select - Read (59h)
      51. 8.2.51  Compensation Temp Host Override - Write (5Ah)
      52. 8.2.52  Compensation Temp Host Override - Read (5Bh)
      53. 8.2.53  ADC Measurements - Read (5Ch)
      54. 8.2.54  Excessive Brightness Control - Write (5Dh)
      55. 8.2.55  Excessive Brightness Control - Read (5Eh)
      56. 8.2.56  ADC Single Measurement - Read (63h)
      57. 8.2.57  Illumination Bin Select - Write (70h)
      58. 8.2.58  Illumination Bin Select - Read (71h)
      59. 8.2.59  TPS99000-Q1 RGB DAC Levels - Write (80h)
      60. 8.2.60  TPS99000-Q1 RGB DAC Levels - Read (81h)
      61. 8.2.61  TPS99000-Q1 RGB Limits - Write (82h)
      62. 8.2.62  TPS99000-Q1 RGB Limits - Read (83h)
      63. 8.2.63  TPS99000-Q1 Blanking Levels - Write (84h)
      64. 8.2.64  TPS99000-Q1 Blanking Levels - Read (85h)
      65. 8.2.65  TPS99000-Q1 TIA1 Trims - Write (86h)
      66. 8.2.66  TPS99000-Q1 TIA1 Trims - Read (87h)
      67. 8.2.67  TPS99000-Q1 TIA1 Gain - Write (88h)
      68. 8.2.68  TPS99000-Q1 TIA1 Gain - Read (89h)
      69. 8.2.69  TPS99000-Q1 TIA1 Capacitance - Write (8Ah)
      70. 8.2.70  TPS99000-Q1 TIA1 Capacitance - Read (8Bh)
      71. 8.2.71  TPS99000-Q1 TIA1 Dark Offsets - Write (8Ch)
      72. 8.2.72  TPS99000-Q1 TIA1 Dark Offsets - Read (8Dh)
      73. 8.2.73  TPS99000-Q1 TIA1 Input Offsets - Write (8Eh)
      74. 8.2.74  TPS99000-Q1 TIA1 Input Offsets - Read (8Fh)
      75. 8.2.75  TPS99000-Q1 DM Pulse Widths - Write (90h)
      76. 8.2.76  TPS99000-Q1 DM Pulse Widths - Read (91h)
      77. 8.2.77  TPS99000-Q1 Drive Mode - Write (92h)
      78. 8.2.78  TPS99000-Q1 Drive Mode - Read (93h)
      79. 8.2.79  TPS99000-Q1 ADC Configuration - Write (94h)
      80. 8.2.80  TPS99000-Q1 ADC Configuration - Read (95h)
      81. 8.2.81  TPS99000-Q1 Illumination Sync Control - Write (96h)
      82. 8.2.82  TPS99000-Q1 Illumination Sync Control - Read (97h)
      83. 8.2.83  TPS99000-Q1 TIA2 Control - Write (98h)
      84. 8.2.84  TPS99000-Q1 TIA2 Control - Read (99h)
      85. 8.2.85  LED Drive Errors - Read (9Ah)
      86. 8.2.86  LED Drive Errors Clear - Write (9Bh)
      87. 8.2.87  TPS99000-Q1 Test Mux Select - Write (9Ch)
      88. 8.2.88  TPS99000-Q1 Test Mux Select - Read (9Dh)
      89. 8.2.89  TPS99000-Q1 TIA1 Offsets - Write (9Eh)
      90. 8.2.90  TPS99000-Q1 TIA1 Offsets - Read (9Fh)
      91. 8.2.91  Flash Data Type Select - Write (A0h)
      92. 8.2.92  Flash Erase Data - Write (A1h)
      93. 8.2.93  Flash Write Data - Write (A2h)
      94. 8.2.94  Flash Read Data - Read (A3h)
      95. 8.2.95  Flash Verify Data - Write (A4h)
      96. 8.2.96  Flash Block Count - Read (A5h)
      97. 8.2.97  Flash Block CRCs - Read (A6h)
      98. 8.2.98  Flash Structure Version - Read (A7h)
      99. 8.2.99  Flash Data Size - Read (A9h)
      100. 8.2.100 System Software Version - Read (B0h)
      101. 8.2.101 Flash Device ID - Read (B1h)
      102. 8.2.102 DLPC230-Q1 Device ID - Read (B2h)
      103. 8.2.103 DMD Device ID - Read (B3h)
      104. 8.2.104 TPS99000-Q1 Device ID - Read (B4h)
      105. 8.2.105 System Temperatures - Read (B5h)
      106. 8.2.106 Current Source Information - Read (B6h)
      107. 8.2.107 Current Display Information - Read (B8h)
      108. 8.2.108 System Information - Read (BAh)
      109. 8.2.109 Flash Interface Rate - Read (BBh)
      110. 8.2.110 Short Status - Read (C0h)
      111. 8.2.111 Error History - Read (C1h)
        1. 8.2.111.1 Information Bits - Command or Communication
        2. 8.2.111.2 Information Bits - System Voltage
        3. 8.2.111.3 Information Bits - DMD High Speed Interface Training
        4. 8.2.111.4 Information Bits - Photo Feedback Test
        5. 8.2.111.5 Information Bits - DMD Memory Test
      112. 8.2.112 Clear Short Status Errors - Write (C2h)
      113. 8.2.113 Clear Error History - Write (C3h)
  11. 9 Commands - Diagnostic Interface
    1. 9.1 Diagnostic Command Read Procedure
    2. 9.2 Command Table
    3. 9.3 Command Definitions
      1. 9.3.1 Read Pre-Fetch - Write (01h)
      2. 9.3.2 Read Activate (02h)
      3. 9.3.3 Diagnostic Interface Status - Read (F0h)
      4. 9.3.4 Diagnostic Interface Status Clear - Write (F1h)
  12. 10Flash Configuration
    1. 10.1 Overview
    2. 10.2 System Mode Overview
    3. 10.3 Calibration Data
      1. 10.3.1 Overview
      2. 10.3.2 Top Level Data Layout
        1. 10.3.2.1  CRC
        2. 10.3.2.2  Size
        3. 10.3.2.3  Version (Major, Minor, Patch)
        4. 10.3.2.4  Temperature Compensation Source
        5. 10.3.2.5  Drive Enable Low Time
        6. 10.3.2.6  Sync Pulse Width
        7. 10.3.2.7  RGB Blanking Percentage
        8. 10.3.2.8  TIA Trim
        9. 10.3.2.9  TIA Capacitance
        10. 10.3.2.10 TIA Dark Offset
        11. 10.3.2.11 TIA Input Offset
        12. 10.3.2.12 TIA Stage X Offset
        13. 10.3.2.13 Tool Information (Info Bytes)
      3. 10.3.3 Calibration Table Data Layout
        1. 10.3.3.1 Temperature Region
      4. 10.3.4 Dimming Level Data Layout
        1. 10.3.4.1 Current Limit
        2. 10.3.4.2 Group X
        3. 10.3.4.3 Blanking Level
        4. 10.3.4.4 CMODE Enable
        5. 10.3.4.5 Sync Period
        6. 10.3.4.6 Compout Low Period
    4. 10.4 Scratchpad Data
      1. 10.4.1 CRC
      2. 10.4.2 Block Number
      3. 10.4.3 Version (Major, Minor, Patch)
      4. 10.4.4 Custom Data
  13.   A Error Codes
    1.     A.1 Boot Application
    2.     A.2 Main Application
  14.   Revision History

3.5.2.1 SPI Read Activate

Table 3-9, Table 3-10, and Figure 3-8 describe the SPI Read Activate protocol.

MOSI Controller Output, Peripheral input (e.g. Host Output, DLPC230 input):

Table 3-9 SPI Read Activate MOSI Bytes
DATA BYTEDESCRIPTION
CMD1-byte write command op-code. This is 02h for Read Activate.
Tag1-byte identifier used to uniquely mark each command sent by host.
LengthLength of the transmitted data payload. This is always 0 for read activate.
CRCCRC or checksum for the read header data. This includes the op-code, tag, and length.

MISO Controller input, Peripheral output (e.g. Host input, DLPC230 output):

Table 3-10 SPI Read Activate MISO Bytes
DATA BYTEDESCRIPTION
CMD (ACK)Echo of the received command op-code from the host controller.
Tag (ACK)Echo of the received tag from the host controller.
LengthRLength of the read header data (Data1a, Data1b). The value is always 2 for read activate.
Data1(a:b)Read header data. Specifies the length of the read return payload (0-256 bytes). LSByte = "a".
CRC-R1CRC or checksum for the header response bytes. This includes the op-code, tag, length, and read return header data (Data1).
Data2(a:n)Read return payload. The number of bytes varies depending on the read command and is specified by the value in Data1(a:b).
CRC-R2CRC or checksum for the read return payload. This only includes the read return payload (Data2) bytes.
DLPC230-Q1 SPI Read Activate Figure 3-8 SPI Read Activate