DLPU125 june 2023
Test pattern generation is provided by VHDL module tpg.vhd along with the sub-modules tpg_trig.vhd and tpg_timing.vhd. A VHDL package tpg_pkg.vhd provides test data constants for various test patterns.
After apps FPGA initialization is complete, 16 test patterns (section Test Pattern Control (0x0014)) are continuously cycled through periodically. Modify the cycle interval field of the test pattern control register (Test Pattern Control (0x0014)) to change the cycling rate. The test pattern control register also provides control bits to disable pattern cycling and continuously display a selected test pattern.
When test patterns are cycling after initialization, pressing momentary push button switch SW3 on the VC-707 board stops the pattern cycling. Successive activation of SW3 selects the next test pattern in the sequence. Pressing the Apps FPGA reset switch on the DLPLCRC910EVM board re-initializes the Apps FPGA and DLP component set and return to auto pattern cycling.
The test pattern generator provides control and addressing to write test patterns into the DMD data buffer. Patterns are read from the data buffer and sent to the DLPC910 under control of the DMD load state machine.