DLPU125 june   2023

 

  1.   1
  2.   DLPC910 Apps FPGA User’s Guide
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Welcome
  5. 2Overview
    1. 2.1 Purpose
    2. 2.2 Apps FPGA Hardware Target
  6. 3Interfaces
    1. 3.1  LVDS high speed data interface to DLPC910
      1. 3.1.1 DLP9000X and DLP9000XUV
      2. 3.1.2 DLP6500
    2. 3.2  Data Load Control Signals to DLPC910
    3. 3.3  DMD Reset and Block Clear Signals to the DLPC910
    4. 3.4  DLPC910 Initialization and Controller Reset Signals
    5. 3.5  Apps FPGA Reset Signal - apps_resetz
    6. 3.6  DLPC910 Status-Info Signals
    7. 3.7  USB GPIF (Interface)
      1. 3.7.1 Apps FPGA Register Address Read-Write Transactions
        1. 3.7.1.1 Apps FPGA Register Address Transaction
        2. 3.7.1.2 Apps FPGA Register Data Write Transaction
        3. 3.7.1.3 Apps FPGA Register Data Read Transaction
      2. 3.7.2 FIFO Write Transaction
    8. 3.8  DLPLCRC910EVM Dip Switch (SW2)
    9. 3.9  VC-707 Dip Switch (SW2)
    10. 3.10 VC-707 Push Button Switches
    11. 3.11 VC-707 Status LEDs
    12. 3.12 DLPLCRC910EVM Apps FPGA Test Points
  7. 4Operation
    1. 4.1 Initialization
      1. 4.1.1 Initialization Prompts
      2. 4.1.2 Init Routine
      3. 4.1.3 GPIO Status LEDs
      4. 4.1.4 Errors
    2. 4.2 Test Pattern Generator (TPG) and Apps Loader - DLP Control
      1. 4.2.1 Test Pattern Generator (TPG)
      2. 4.2.2 DMD Data Buffer
      3. 4.2.3 DMD Load State Machine
      4. 4.2.4 DMD Reset State Machine
      5. 4.2.5 DMD Load Parameters
      6. 4.2.6 Synchronization Pulse
    3. 4.3 User DLP Control
      1. 4.3.1 DLP6500 (1920 x 1080) User Image Display Example (Global)
      2. 4.3.2 DLP9000X (2560 x 1600) User Image Display Example (Global)
      3. 4.3.3 Load4 - Using with DLP6500 DMD
      4. 4.3.4 USB GPIF FIFO Data Writes
      5. 4.3.5 External Trigger
    4. 4.4 USB GPIF (Operation)
    5. 4.5 Clocks and Resets
      1. 4.5.1 Reference Clocks
      2. 4.5.2 Clk50 and Clk100
      3. 4.5.3 DLP Clocks
      4. 4.5.4 USB GPIF Clock
      5. 4.5.5 Logic Resets
      6. 4.5.6 Clock Domain Crossings (CDC)
    6. 4.6 Switch Debounce
  8. 5USB GPIF Registers
    1. 5.1 Register Definitions
      1. 5.1.1  Status (0x000C)
      2. 5.1.2  Data Loading Control (0x0010)
      3. 5.1.3  Test Pattern Control (0x0014)
      4. 5.1.4  Test Row Address (0x0018) - [Unused]
      5. 5.1.5  Loader Reset Type (0x001C)
      6. 5.1.6  Type and Version (0x0020)
      7. 5.1.7  User Image Buffer Write Settings (0x0024)
      8. 5.1.8  USB GPIF FIFO Read Burst Size (0x0028) - [Obsolete]
      9. 5.1.9  User Row Command Register (0x002C)
      10. 5.1.10 User Block Command Register (0x0030)
      11. 5.1.11 Loader Row Control (0x0034)
      12. 5.1.12 Loader Load Interval (0x0038)
      13. 5.1.13 Loader Expose Time (0x003C)
      14. 5.1.14 Address Write (0x003F) - [Unused]
      15. 5.1.15 Loader Control (0x0040)
      16. 5.1.16 Park [PWR_FLOAT] (0x0044)
      17. 5.1.17 External Trigger Status (0x0048)
      18. 5.1.18 FPGA Build Date (0x0080)
      19. 5.1.19 Major-Minor Revision (0x0084)
      20. 5.1.20 Fixed Value FPGA Identifier (0x0088)
      21. 5.1.21 Test Register (0x008C)
  9. 6FPGA Configuration
  10. 7Apps FPGA Source Files and Compilation
    1. 7.1 Design Tools
    2. 7.2 Source Files
      1. 7.2.1 Primary VHDL and IP Modules
      2. 7.2.2 Modules with Multiple Instantiations
      3. 7.2.3 VHDL Packages
      4. 7.2.4 Vivado Constraints
      5. 7.2.5 Memory IP Initialization Files
        1. 7.2.5.1 Look Up Tables
    3. 7.3 Building the Apps FPGA Code
      1. 7.3.1 Source Code
        1. 7.3.1.1 Source Folder
      2. 7.3.2 Creating the Vivado Project
      3. 7.3.3 Compiling the Design
      4. 7.3.4 Simulation
        1. 7.3.4.1 Test Benches
        2. 7.3.4.2 Steps to Simulate a Module
  11. 8Related Documentation from Texas Instruments
  12. 9Appendix
    1. 9.1 Abbreviations and Acronyms
    2. 9.2 Information About Cautions and Warnings

5.1.13 Loader Expose Time (0x003C)

Address BITS Description Default R/W
0x003C (31:16) Not used zeros R/W
(15:0) Expose time counts(1) 0x0000 R/W
(1) When a trigger occurs, the Loader sends the pattern buffer to the DMD and performs a reset to display the pattern. Expose time is wait time added after the reset is complete before the Loader waits for the next trigger. Expose time is measured in row cycle counts:
  • For DLP9000X and DLP9000XUV DMDs, row cycles are 20 dclk cycles long at 400 MHz or 480 MHz (50 ns or 41.67 ns).
  • For DLP65000 DMDs, row cycles are 32 dclk cycles long at 400 MHz (80 ns).
For example with the default Load Interval of 400 us no change will be seen in the pattern load frequency until the total of load time plus reset time plus expose time exceeds a multiple of 400 us. Therefore, the effective step size is the Loader Load Interval (0x0038).