DLPU125 june 2023
Per AMD - Xilinx recommendation for 7 series FPGAs, all Apps FPGA clocked logic is coded with synchronous resets. There are a few exceptions to this rule, such as a loss of lock reset for a PLL, which is asserted asynchronously, de-asserted synchronously.
The synchronous reset signal names generally use names similar to the clock for a
given domain. For example, rstu
is the synchronous reset for the
clku
domain.