DLPU125 june 2023
Address | BITS | Description | Default(1) | R/W |
---|---|---|---|---|
0x000C | (31:16) | not used | 0x0000 | R |
15 | not used | ‘0’ | R | |
14 | not used | ‘0’ | R | |
13 | not used | ‘0’ | R | |
12 | not used | ‘0’ | R | |
11 | not used | ‘0’ | R | |
10 | not used | ‘0’ | R | |
9 | not used | ‘0’ | R | |
8 | not used | ‘0’ | R | |
7 | not used | ‘0’ | R | |
6 | not used | ‘0’ | R | |
5 | DLOK: 1 = DLP (DMD) PLL locked. 0 = not locked | ‘1’ | R | |
4 | SLOK: 1 = system PLL locked. 0 = not locked | ‘1’ | R | |
3 | RACT: rst_active signal from DLPC910(2) | ‘0’ or ‘1’ | R | |
2 | IRQ – DMD_IRQ signal from DLPC910(2) | ‘0’ | R | |
1 | ECP: ecp2_finished signal from DLPC910(2) | ‘1’ | R | |
0 | CAL: 1 = apps FPGA is sending training patterns to DLPC910 | ‘0’ | R |