DLPU125 june 2023
For internal DLP control logic, the Apps FPGA uses a clock that is ¼ the frequency of
the DLPC910 high speed interface clock. This clock is named clkd
in
the VHDL code.
The DLPC910 high speed interface is a double data rate (DDR) interface, resulting in an 8:1, high-speed to internal, clock ratio. This allows the Apps FPGA to use AMD - Xilinx OSERDESE2 DDR primitives for data - control output. For every Apps FPGA internal clock rising edge, 8 data bits are loaded into the OSERDESE2 primitives, for shifting out at the high-speed DDR clock rate.
The Apps FPGA is required to support
two different high-speed interface clock frequencies, 400 MHz and 480 MHz. Separate
PLLs (AMD / Xilinx IP) are used so that exact clock frequencies can be created. One
PLL generates 100/400 MHz clocks, the other PLL generates 120/480 MHz clocks. Both
PLLs use the 200 MHz sysclk_p/n
for their reference clock, and both
PLLs run continuously.
Clock mux primitives are used to create both clkd
and
clkd4x
(clkd4x
is phase-aligned to
clkd
and is used by OSERDESE2 primitives). The 100 or 120 MHz
clock is selected by a single clock mux to create clkd
. The 400 or
480 MHz clock is selected by another clock mux to create clkd4x
.
Clock selection is performed once during initialization by the init-run-park state
machine. After clock selection, the init-run-park state machine issues reset to the
OSERDESE2 primitives and to the Apps FPGA logic.