Address |
BITS |
Description |
Default |
R/W |
0x0040 |
(31:2) |
Not used |
zeros |
R/W |
1 |
Free-run(1) |
0 |
R/W |
0 |
Loader enable(2) |
1 |
R/W |
(1) When set to ‘1’, free-run bit
tells the test pattern loader to run at maximum rate, ignoring the load
trigger.
(2) When loader enable is set to
‘1’, apps FPGA test pattern loader sends test pattern images to the DLP chip
set. When ‘0’, test pattern loading stops, and DLP chip set is controlled
through the USB GPIF. When loader enable bit transitions from ‘1’ to ‘0’, the
DMD image is cleared using block clear commands, after which the user is given
control of the DLP chip set through the USB GPIF.