Design Description

This cookbook design describes how to expand the input range of a SAR ADC with an integrated analog front end (AFE) and decrease the loss of accuracy by implementing a two-point calibration method. This design uses the ADS8598H at the full scale range of ±10V and expands the accessible input range to ±40V. This allows for a wider input range to be used without extra analog circuitry to step down the voltage; instead a simple voltage divider is used to interact with the AFE of the device to step down the voltage near the device input. A calibration method can be implemented to eliminate any error that could occur.

A similar cookbook design, Reducing Effects of External RC Filter on Gain and Drift Error for Integrated AFE: ±10V, up to 200kHz, 16 bit, explaining how to measure introduced drift from external components can prove to also be helpful in this application. Increasing the input range that the ADC can measure proves useful in end equipment such as: Data Acquisition Modules, Multi Function Relays, AC Analog Input Modules, and Control Units for Rail Transport.

Specifications

Design Notes

1. Use low-drift resistors to decrease any error introduced due to temperature drift, such as 50ppm/°C with 1% tolerance or better. Note that as resistor values increase to 1MΩ and beyond, low-drift precision resistors can become more expensive.
2. An input filter is frequently required for this configuration. Placing it directly after the large input impedance can cause errors because of the capacitor leakage. If an input filtering capacitor is needed, an alternate schematic is shown in this design.

Component Selection

The internal impedance of the device is 1MΩ, the external resistor is selected based on the desired extended input range (Vin), in this case ±40V. This external resistor forms a voltage divider with the internal impedance of the device, stepping down the input voltage at the ADC input pins (Vin_ADC) within the device input range of ±10V.

1. Rearrange the voltage divider equation to solve for the external resistor value. This same equation can later be used to calculate the expected Vin_ADC value from the input voltage.
   
2. Solve for the external resistor value for the desired extended input voltage. Vin = ±40V, Rin = 1M Ω
   

The input can be extended to a variety of ranges, depending on what external resistor value is used.

Non-Calibrated Measurements

Different DC input values ranging through the full ±40-V scale were used to measure the ADC voltage input and the accuracy of the measurement. The following equation shows how to calculate the analog voltage read by the ADC. Here the FSR is the system full scale range which is 40V in this case. The factor of 2 is included because this is a bipolar input where the input range is actually ±40V which is a range of 80V. Vout_ADC for this equation will range ±40V, which corresponds to the system input.

The percent error of the value is calculated using the next equation:

Two-Point Calibration

Calibration can be applied in order to eliminate the reading error introduced by the external resistor. The two-point calibration applies and samples two test signals at 0.25V from the full scale input range within the linear range of the ADC. These sample measurements are then used to calculate the slope and offset of the linear transfer function. Calibration will eliminate both the gain error introduced by the external resistor and the internal device gain error.

1. Apply test signal at –39V:

   Vmin	Measured Code
   –39V	–128689

2. Apply test signal at 39V:

   Vmax	Measured Code
   39V	128701

3. Calculate slope and offset calibration coefficients:
   
   
4. Apply calibration coefficients to all subsequent measurements:
   

Two-Point Calibration Measurements

Calibration Coefficients

m = 3299.872; b = 6.008

When calibration is applied the readings error is dramatically reduced.

Alternate Schematic With Filter Capacitor

Due to the high-value resistors used, introducing a capacitor would lead to significant impact in readings, such as increase drift experienced. This is because of the capacitor leakage. This leakage will vary over time and temperature and will generate errors that are difficult to calibrate out. If an input filter is needed, the alternate schematic can be used to implement it. The capacitor is placed with a balanced resistor-capacitor filter before the external resistors in relation to the input signal.

Alternate Schematic With Filter Capacitor - Component Selection

External anti-aliasing RC filters reduce noise and protect from electrical overstress. A balanced RC filter configuration is required for better common-mode noise rejection; matching external resistors are added to both the negative and positive input paths. These external resistors should also be low-drift resistors as stated in the Design Notes.

1. Choose a value of R based on the desired cutoff frequency. This example uses a cutoff frequency of 320Hz, and a resistor value of 10kΩ.

   R = 10kΩ

2. Select C_FIL
   

   Nearest standard capacitor value available, C_FIL= 24nF

Design Featured Devices