SBAA247 Circuit design

Input	ADC Input	Digital Output ADS7042
VinDiffMin = –20V	CH_x = +10V	7FFF_H, or 32767₁₀
VinDiffMax = +20V	CH_x = –10V	8000_H , or 32768₁₀

Power Supplies
AVDD	DVDD	V_CC (HVDD)	V_SS (HVSS)
5.0V	3.3V	+15V	–15V

Design Description

This design shows a design to drive high-voltage SAR ADC to implement data capture for high-voltage fully differential signal which can have a wide common-mode voltage range depended on the power supply and input amplitude signal of the amplifier. A general high-voltage precision amplifier performs the differential to single-ended conversion and drives high-voltage SAR ADC single-ended input scale of ±10V at highest throughput. This type of application is popular in end equipment such as: Multi-Function Relays, AC Analog Input Modules, and Control Units for Rail Transport. The values in the component selection section can be adjusted to allow for different level differential input signal, different ADC data throughput rates, and different bandwidth amplifiers.

Specifications

Specification	OPA827 Calculated	OPA827 Simulated	OPA192 Calculated	OPA192 Simulated
Common Mode Input Range (with Vdif = ±20V)	±26V	±26V	±35V	±35V
Transient ADC Input Settling Error	< 1/2LSB (< 152µV)	0.002 LSB (0.568µV)	< 1/2LSB (< 152µV)	0.006 LSB (1.86µV)
Phase Margin of driver	> 45°	67.1°	> 45°	68.6°
Noise (at ADC Input)	14.128µVrms	15.88µVrms	5.699µVrms	6.44µVrms

Design Notes

Determine the amplifier gain based on the differential input signal level, the ADC’s configuration for input range. This is covered in the component selection section.
Determine amplifier’s linear range based on common mode voltage, input swing, and power supplies. This is covered in the component selection section.
In this design circuit, the common-mode voltage of the input signal can be any value in the range of V_InputCM . The derivation of this range is provided in the component selection section for the OPA827 and OPA192.
Select COG capacitors to minimize distortion.
Use 0.1% 20ppm/°C film resistors or better for good accuracy, low gain drift, and to minimize distortion. Review Statistics Behind Error Analysis for methods to minimize gain, offset, drift, and noise errors.
Refer to Introduction to SAR ADC Front-End Component Selection for an explanation of how to select Rfilt and Cfilt for best settling and AC performance. These component values are dependent on the amplifier bandwidth, data converter sampling rate, and data converter design. The values shown here provide good settling and AC performance for the amplifier and data converter in this example. If the design is modified, select a different RC filter.

Component Selection

Find the gain based on differential input signal and ADC full-scale input range.
$G a i n_{O P A} = \frac{\pm V_{A D C (r a n g e)}}{\pm V_{D i f I n (r a n g e)}} = \frac{\pm 10 V}{\pm 20 V} = 0.5 V / V$
Find standard resistor values for differential gain. Use the Analog Engineer's Calculator ("Amplifier and Comparator\Find Amplifier Gain" section) to find standard values for Rf/Rg ratio.
$G a i n_{O P A} = \frac{R_{f}}{R_{g}} = \frac{5.05 k Ω}{10.1 k Ω} = 0.5$
Find the amplifier’s maximum and minimum input for linear operation (that is, the common mode range of the amplifier, V_{cm_amp}). For this example, the OPA827 is used.
$V_{-} + 3 V < V_{c m_o p a} < V_{+} - 3 V from the OPA827 common mode specification$
$- 12 V < V_{c m_o p a} < 12 V f o r \pm 15 V s u p p l i e s$
Calculate the maximum common-mode voltage range based on the input range and previously shown configuration of the amplifier. Refer to the schematic diagram on the first page for better understanding of how V_{cm_opa}, V_InputCM, and V_dif relate to the circuit.
$V_{c m_o p a} = (V_{I n p u t C M} \pm \frac{V_{d i f}}{2}) \cdot (\frac{R_{f}}{R_{f} + R_{g}})$
$V_{c m_o p a M i n} \cdot (\frac{R_{f} + R_{g}}{R_{f}}) + \frac{V_{d i f}}{2} < V_{I n p u t C M} < V_{c m_o p a M a x} \cdot (\frac{R_{f} + R_{g}}{R_{f}}) - \frac{V_{d i f}}{2}$
Solve the equation for the input common-mode range V_InputCM for the amplifier. For this example (OPA827), the common mode input can be ±26V with a ±20-V differential input. Using the same method on OPA192 shows a common mode range of ±35V with a ±20-V differential input. Exceeding this common-mode range distorts the signal. Note that this common-mode range was calculated using ±15-V power supplies. The common mode range can be extended by increasing the supply (maximum ±18V).
$V_{c m_o p a M i n} \cdot (\frac{R_{f} + R_{g}}{R_{f}}) + \frac{V_{d i f}}{2} < V_{I n p u t C M} < V_{c m_o p a M a x} \cdot (\frac{R_{f} + R_{g}}{R_{f}}) - \frac{V_{d i f}}{2}$
$(- 12 V) \cdot (\frac{5.05 k Ω + 10.1 k Ω}{5.05 k Ω}) + \frac{20 V}{2} < V_{I n p u t C M} < (12 V) \cdot (\frac{5.05 k Ω + 10.1 k Ω}{5.05 k Ω}) - \frac{20 V}{2}$
$- 26 V < V_{I n p u t C M} < 26 V$
Find the value for Cf that achieves the desired closed-loop bandwidth. In this example, users need a 10kHz bandwidth. Note: if users adjust the bandwidth, then users need to verify the charge bucket filter settling (C_filt and R_filt) as the closed-loop bandwidth effects settling.
$C_{f} = \frac{1}{2 \cdot π \cdot R_{f} \cdot f_{c}} = \frac{1}{2 \cdot π \cdot (5.05 k Ω) \cdot (10 k H z)} = 3.1 n F o r 3 n F s \tan d a r d v a l u e$
Find the value for Cfilt and Rfilt using TINA SPICE and the methods described in Introduction to SAR ADC Front-End Component Selection. The value of Rfilt and Cfilt shown in this document works for these circuits; however, if users use different amplifiers or different gain settings, then users must use TINA SPICE to find new values.

DC Transfer Characteristics

The following graph shows a linear output response for inputs from differential –20V to +20V. The full-scale range (FSR) of the ADC falls within the linear range of the op amp. Refer to Determining a SAR ADC's Linear Range when using Operational Amplifiers for detailed theory on this subject.

AC Transfer Characteristics

The bandwidth is simulated to be 10.58kHz and the gain is –6.038dB which is a linear gain of 0.5V/V. See the Op Amps: Bandwidth 1 video for more details on this subject.

Transient ADC Input Settling Simulation Highest Sampling rate – 510ksps on ADS8568+OPA827

The following simulation shows settling to a 20V DC input signal with OPA827. This type of simulation shows that the sample and hold kickback circuit is properly selected to within ½ of a LSB (152µV). For detailed theory on this subject, refer to Introduction to SAR ADC Front-End Component Selection.

Transient ADC Input Settling Simulation Lower Sampling rate – 200ksps on ADS8568+OPA192

The following simulation shows settling to a 20V DC input signal with OPA192. This type of simulation shows that the sample and hold kickback circuit is properly selected to within ½ of a LSB (152µV).

Noise Calculation

This section demonstrates a full-noise analysis including resistor noise. Also, look at the noise below f_c (Noise Gain = 1.5), and the noise above f_c (noise Gain = 1). In this example, the noise is dominated by wide band amplifier noise so the resistors do not contribute significantly. However, in many cases the resistor noise can be important, so the full noise calculation is provided. For more detailed theory on this subject, refer to Calculating the Total Noise for ADC Systems and Op Amps: Noise 1.

Bandwidth for feedback loop:

f_{c} = \frac{1}{2 \cdot π \cdot R_{f} \cdot C_{f}} = \frac{1}{2 \cdot π \cdot (5.05 kΩ) \cdot (3 nF)} = 10.6 k H z

Noise from OPA827: 3.8nV/rtHz

E_{n_a m p 1} = e_{n_827} \cdot \sqrt{K_{n} \cdot f_{c}} = (3.8 n V / \sqrt{H z}) \cdot \sqrt{(1.57) \cdot (10.6 k H z)} = 490 n V r m s

Thermal noise density from feedback loop (R_f1 and R_g1 ) and RC non-inverting input (R_f2 and R_g2 ):

R_{e q} = R_{f} | | R_{g} = \frac{R_{f} \cdot R_{g}}{R_{f} + R_{g}} = \frac{(5.05 k Ω) \cdot (10.1 k Ω)}{5.05 k Ω + 10.1 k Ω} = 3.37 k Ω

e_{n_f e e d b a c k} = \sqrt{4 \cdot K_{n} \cdot T_{K} \cdot R_{e q}} = \sqrt{4 \cdot (1.38 \cdot 10^{- 23}) \cdot (298) \cdot (3.37 k Ω)} = 7.4 n V / \sqrt{H z}

E_{n_f e e d b a c k} = e_{n_f e e d b a c k} \cdot \sqrt{K_{n} \cdot f_{c}} = (7.4 n V / \sqrt{H z}) \cdot \sqrt{(1.57) \cdot (10.6 k H z)} = 0.955 μ V r m s

Noise from resistors on the non-inverting input is the same as noise from the feedback resistors.

E_{n_i n p u t} = E_{n_f e e d b a c k} = 0.955 μ V r m s

Total noise (in gain) referred to output of amplifier:

E_{n_b e l o w_f c} = (G_{n}) \sqrt{{E_{n_a m p 1}}^{2} + {E_{n_f e e d b a c k}}^{2} + {E_{n_i n p u t}}^{2}}

E_{n_b e l o w_f c} = (1.5) \sqrt{(0.49 μ V)^{2} + (0.995 μ V)^{2} + (0.995 μ V)^{2}} = 2.155 μ V r m s

Noise above fc is limited by the output filter (cutoff given below):

f_{o u t p u t} = \frac{1}{2 \cdot π \cdot R_{f i l t} \cdot C_{f i l t}} = \frac{1}{2 \cdot π \cdot (49.9 Ω) \cdot (370 p F)} = 8.6 M H z

E_{n_a b o v e_f c} = e_{n_827} \cdot \sqrt{K_{n} \cdot f_{o u t p u t}} = (2.8 n V / \sqrt{H z}) \cdot \sqrt{(1.57) \cdot (8.6 M H z)} = 13.963 μ V

Total noise applied to input of the ADC:

E_{n_t o t a l} = \sqrt{{E_{n_b e l o w_f c}}^{2} + {E_{n_a b o v e_f c}}^{2}} = \sqrt{(2.155 μ V)^{2} + (13.963 μ V)^{2}} = 14.128 μ V r m s

Noise Simulation

The simulated results compare well with the calculated results (that is, simulated = 15.88µVrms, calculated = 14.128µVrms).

Stability Test

The phase margin for this OPA827 driving circuit is 67.1°, which meets the >45° requirement and is stable. For detailed theory explaining stability analysis, refer to Op Amps: Stability 1.

Design Featured Devices

Device	Key Features	Link	Similar Devices
ADS8568 ⁽¹⁾	16-bit, 8 Channel Simultaneous-Sampling, Bipolar-Input SAR ADC	www.ti.com/product/ADS8568	www.ti.com/adcs
OPA827	Low-Noise, High-Precision, JFET-Input Operational Amplifier	www.ti.com/product/OPA827	www.ti.com/opamp
OPA192	High-Voltage, Rail-to-Rail Input/Output, 5µV, 0.2µV/°C, Precision operational amplifier	www.ti.com/product/OPA192	www.ti.com/opamp

(1) The ADS8568 has integrated a precision voltage reference which can meet most design requirements, but an external REF5050 can be directly connected to the ADS8568 without any additional buffer because the ADS8568 has a built in internal reference buffer for every ADC channel pair. Also, REF5050 has the required low noise and drift for precision SAR applications. C1 is added to balance CMRR (common-mode rejection ratio). Clean analog power supplies are required to achieve best performance specified in the data sheet of the ADC.

Design References

For TI's comprehensive circuit library, refer to Analog Engineer's Circuit Cookbooks.

Link to Key Files (TINA)

Design files for this circuit – http://www.ti.com/lit/zip/sbac180.