Input | ADC Input | Digital Output ADS7042 |
---|---|---|
VinMin = 0V | AIN_P = 0V, AIN_M = 0V | 000H or 010 |
VinMax = 3.3V | AIN_P = 3.3V, AIN_M = 0V | FFFH or 409610 |
AVDD | Vee | Vdd |
---|---|---|
3.3V | –0.3V | 4.5V |
This design shows an low-power amplifier being used to drive a SAR ADC that consumes only nW of power during operation. This design is intended for systems collecting sensor data and require a low-power signal chain which only burns single-digit µW of power. PIR sensors, gas sensors, and blood glucose monitors are a few examples of power-sensitive systems that benefit from this SAR ADC design. The values in the component selection section can be adjusted to allow for different data throughput rates and different bandwidth amplifiers. Low-Power Sensor Measurements: 3.3V, 1ksps, 12-bit Single-Ended, Single Supply shows a simplified version of this circuit where the negative supply is grounded. The –0.3-V negative supply in this example is used to achieve the best possible linear input signal range. See SAR ADC Power Scaling for a detailed description of trade-offs in low-power SAR design.
Specification | Calculated | Simulated | Measured |
---|---|---|---|
Transient ADC Input Settling (1ksps) | < 0.5 × LSB = 402µV | 41.6µV | N/A |
AVDD Supply Current (1ksps) | 230nA | N/A | 214.8nA |
AVDD Supply Power (1ksps) | 759nW | N/A | 709nW |
VDD OPAMP Supply Current | 450nA | N/A | 431.6nA |
VDD OPAMP Supply Power | 2.025µW | N/A | 1.942µW |
AVDD + VDD System Power (1ksps) | 2.784µW | N/A | 2.651µW |
The following graph shows a linear output response for inputs from 0 to 3.3V. The full-scale range (FSR) of the ADC falls within the linear range of the op amp. Refer to Determining a SAR ADC’s Linear Range when using Operational Amplifiers for detailed theory on this subject.
The bandwidth simulation includes the effects of the amplifier output impedance and the RC charge bucket circuit (Rfilt and Cfilt).The bandwidth of the RC circuit is shown in the following equation as 1.56kHz. The simulated bandwidth of 2 kHz includes effects from the output impedance interacting with the impedance of the load. See TI Precision Labs - Op Amps: Bandwidth 1 for more details on this subject.
The following simulation shows settling to a 3-V DC input signal. This type of simulation shows that the sample and hold kickback circuit is properly selected to within ½ of an LSB (402µV). Refer to Introduction to SAR ADC Front-End Component Selection for detailed theory on this subject.
This section walks through a simplified noise calculation for a rough estimate. The resistor noise in this calculation is neglected because it is attenuated for frequencies greater than 10 kHz.
Note that the calculated and simulated values match well. Refer to Calculating the Total Noise for ADC Systems for detailed theory on this subject.
This performance was measured on a modified version of the ADS7042EVM with a 10-Hz input sine wave. The AC performance indicates SNR = 71.0dB, THD = –82.4dB, and ENOB (effective number of bits) = 11.51, which matches well with the specified performance of the ADC, SNR = 70dB and THD = –80dB. This test was performed at room temperature. See Introduction to Frequency Domain for more details on this subject.
Device | Key Features | Link | Similar Devices |
---|---|---|---|
ADS7042(1) | 12-bit resolution, SPI, 1-Msps sample rate, single-ended input, AVDD reference input range 1.6V to 3.6V. | 12-Bit 1MSPS Ultra-Low-Power Ultra-Small-Size SAR ADC With SPI Interface | Analog-to-digital converters (ADCs) |
LPV811(2) | 8-kHz bandwidth, rail-to-rail output, 450-nA supply current, unity gain stable | Single Channel 450nA Precision Nanopower Operational Amplifier | Operational amplifiers (op amps) |
Texas Instruments, SBAM342 circuit, design files
Changes from Revision A (March 2019) to Revision B (September 2024)
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