Design Goals

Design Description

This design shows an low-power amplifier being used to drive a SAR ADC that consumes only nW of power during operation. This design is intended for systems collecting sensor data and require a low-power signal chain which only burns single-digit µW of power. PIR sensors, gas sensors, and blood glucose monitors are a few examples of power-sensitive systems that benefit from this SAR ADC design. The values in the component selection section can be adjusted to allow for different data throughput rates and different bandwidth amplifiers. Low-Power Sensor Measurements: 3.3V, 1ksps, 12-bit Single-Ended, Single Supply shows a simplified version of this circuit where the negative supply is grounded. The –0.3-V negative supply in this example is used to achieve the best possible linear input signal range. See SAR ADC Power Scaling for a detailed description of trade-offs in low-power SAR design.

Design Notes

1. Determine the linear range of the op amp based on common mode, output swing, and linear open loop gain specification. This is covered in the component selection section.
2. Select a COG (NPO) capacitor for Cfilt to minimize distortion.
3. The TI Precision Labs – ADCs training video series covers methods for selecting the charge bucket circuit Rfilt and Cfilt (see Introduction to SAR ADC Front-End Component Selection). These component values are dependent on the amplifier bandwidth, data converter sampling rate, and data converter design. The values shown here provide good settling and AC performance for the amplifier and data converter in this example. Modifying the design requires selection of a different RC filter.

Component Selection

1. Select a low-power op amp:
   • Supply current < 0.5µA
   • Gain bandwidth product > 5kHz (five times the sampling rate)
   • Unity gain stable
   • LPV811 – 450-nA supply current, 8-kHz gain bandwidth product, unity gain stable
2. Find op amp maximum and minimum output for linear operation:
   ${\mathrm{V}}_{\mathrm{ee}}+0\mathrm{V}<{\mathrm{V}}_{\mathrm{out}}<{\mathrm{V}}_{\mathrm{dd}}-0.9\mathrm{V} \mathrm{from} \mathrm{LPV}811 {\mathrm{V}}_{\mathrm{cm}} \mathrm{specification}$
   ${\mathrm{V}}_{\mathrm{ee}}+10\mathrm{mV}<{\mathrm{V}}_{\mathrm{out}}<{\mathrm{V}}_{\mathrm{dd}}-10\mathrm{mV} \mathrm{from} \mathrm{LPV}811 \mathrm{Vout} \mathrm{swing} \mathrm{specification}$
   ${\mathrm{V}}_{\mathrm{ee}}+0.3\mathrm{V}<{\mathrm{V}}_{\mathrm{out}}<{\mathrm{V}}_{\mathrm{dd}}-0.3\mathrm{V} \mathrm{from} \mathrm{LPV}811 \mathrm{Aol} \mathrm{linear} \mathrm{region} \mathrm{specification}$
3. Typical power calculations (at 1ksps) with expected values. See SAR ADC Power Scaling for a detailed description of trade-offs in low-power SAR design:
   ${\mathrm{P}}_{\mathrm{AVDD}}={\mathrm{I}}_{\mathrm{AVDD\_AVG}}\times \mathrm{AVDD}=230\mathrm{nA}\times 3.3\mathrm{V}=759\mathrm{nW}$
   ${\mathrm{P}}_{\mathrm{LPV}811}={\mathrm{I}}_{\mathrm{LPV}811}\times ({\mathrm{V}}_{\mathrm{dd}}-{\mathrm{V}}_{\mathrm{ee}})=450\mathrm{nA}\times [4.5\mathrm{V}-(-0.3\mathrm{V}\left)\right]=2.16\mathrm{\mu W}$
   ${\mathrm{P}}_{\mathrm{total}}={\mathrm{P}}_{\mathrm{AVDD}}+{\mathrm{P}}_{\mathrm{LPV}811}=759\mathrm{nW}+2.16\mathrm{\mu W}=2.919\mathrm{\mu W}$
4. Typical power calculations (at 1ksps) with measured values:
   ${\mathrm{P}}_{\mathrm{AVDD}}={\mathrm{I}}_{\mathrm{AVDD\_AVG}}\times \mathrm{AVDD}=214.8\mathrm{nA}\times 3.3\mathrm{V}=708.8\mathrm{nW}$
   ${\mathrm{P}}_{\mathrm{LPV}811}={\mathrm{I}}_{\mathrm{LPV}811}\times ({\mathrm{V}}_{\mathrm{dd}}-{\mathrm{V}}_{\mathrm{ee}})=431.6\mathrm{nA}\times [4.5\mathrm{V}-(-0.3\mathrm{V}\left)\right]=2.071\mathrm{\mu W}$
   ${\mathrm{P}}_{\mathrm{total}}={\mathrm{P}}_{\mathrm{AVDD}}+{\mathrm{P}}_{\mathrm{LPV}811}=708.8\mathrm{nW}+2.071\mathrm{\mu W}=2.780\mathrm{\mu W}$
5. Find Rfilt and Cfilt to allow for settling at 1ksps. Refer to Refine the Rfilt and Cfilt Values (a Precision Labs video) for the algorithm to select Rfilt and Cfilt. The final value of 200kΩ and 510pF proved to settle to well below ½ of a least significant bit (LSB).

DC Transfer Characteristics

The following graph shows a linear output response for inputs from 0 to 3.3V. The full-scale range (FSR) of the ADC falls within the linear range of the op amp. Refer to Determining a SAR ADC’s Linear Range when using Operational Amplifiers for detailed theory on this subject.

AC Transfer Characteristics

The bandwidth simulation includes the effects of the amplifier output impedance and the RC charge bucket circuit (R_filt and C_filt).The bandwidth of the RC circuit is shown in the following equation as 1.56kHz. The simulated bandwidth of 2 kHz includes effects from the output impedance interacting with the impedance of the load. See TI Precision Labs - Op Amps: Bandwidth 1 for more details on this subject.

Transient ADC Input Settling Simulation

The following simulation shows settling to a 3-V DC input signal. This type of simulation shows that the sample and hold kickback circuit is properly selected to within ½ of an LSB (402µV). Refer to Introduction to SAR ADC Front-End Component Selection for detailed theory on this subject.

Noise Simulation

This section walks through a simplified noise calculation for a rough estimate. The resistor noise in this calculation is neglected because it is attenuated for frequencies greater than 10 kHz.

Note that the calculated and simulated values match well. Refer to Calculating the Total Noise for ADC Systems for detailed theory on this subject.

Design Featured Devices

Link to Key Files (TINA)

Texas Instruments, SBAM342 circuit, design files