Design Description

This design explains how sensor outputs can be directly interfaced with a SAR ADC input. In applications such as wireless environmental sensors, gas detectors, and smoke and heat detectors, the input is very slow-moving and the sensor output voltage is sampled at fairly slower speeds (10ksps or so). In such or similar systems, the sensor output can be directly interfaced with the SAR ADC input without the need for a driver amplifier to achieve a small form-factor, low-cost design.

Interfacing Sensor Output Directly to a SAR ADC

The following figure shows a typical application diagram for interfacing a sensor directly to a SAR ADC input without the use of a driver amplifier. The sensor block highlights the Thevenin equivalent of a sensor output. Voltage source, V_TH, is the Thevenin-equivalent voltage and source resistance R_TH is the Thevenin-equivalent impedance. Most sensor data sheets provide the Thevenin model of the sensor from which the value of the series impedance can be easily calculated.

Specifications

Design Note

1. Determine source impedance of input signal. Calculate the RC time constant of the input source impedance and filter capacitor (known value).
2. Determine the minimum acquisition time required for the input signal to settle for a given source impedance and the filter capacitor combination.
3. Select COG capacitors to minimize distortion.
4. Use 0.1% 20ppm/°C film resistors or better for good gain drift and to minimize distortion.

Component Selection for ADC Input Settling

SAR ADCs can be directly interfaced with sensors when the analog input source is capable of driving the switched capacitor load of a SAR ADC and settling the analog input signal to within ½ of an LSB within the acquisition time of the SAR ADC. To achieve this, the external RC filter (R_TH and C_FLT) must settle within the acquisition time (t_ACQ) of the ADC. The relationship between the ADC acquisition time and RC time constant of the external filter is:

where

• Ԏ_FLT = R_TH × C_FLT
• k is the single pole time constant for N bit ADC

The following design example values are given in the table on page 1:

K = 11 (Single pole time constant multiplier for 14-bit ADC) – More information is found on pages 96 and 97 of the Analog Engineer’s Pocket Reference Guide e-Book.

Minimum acquisition time required for proper settling is calculated using this equation:

For more information on SAR ADCs and front end design for SAR ADCs, refer to theIntroduction to SAR ADC Front-End Component Selection video.

Transient Input Settling Simulation using TI-TINA

The following figure shows the settling of an ADS7056 ADC given a 3.15-V DC input signal. This type of simulation shows that the sample and hold kickback circuit is properly selected. Refer to Refine the Rfilt and Cfilt Values in the TI Precision Labs - ADCs training video series for detailed theory on this subject.

Increasing Acquisition Time of SAR ADC for Input Signal Settling

The acquisition time of a SAR ADC can be increased by reducing the throughput in the following ways:

1. Reducing the SCLK frequency to reduce the throughput.
2. Keeping the SCLK fixed at the highest permissible value and increasing the CS high time.

The following table lists the acquisition time for the previous two cases for the ADS7056 SAR ADC operating at 10ksps throughput (tcycle = 100µs). Case 2 provides a longer acquisition time for the input signal to settle because of the increased frequency of the SCLK given a fixed conversion and cycle time.

The following table shows a performance comparison between an 8-, 10-, 12-, and 14-bit ADC with respect to sampling speed and effective number of bits (ENOB) when a sensor output with an output impedance of 10kΩ is directly interfaced with the ADC input. As expected, the ENOB degrades with higher sampling rates because the acquisition time decreases.

Performance Achieved at Different Throughput Rates with Different Source Impedance

The following figure provides the ENOB achieved from the ADS7056 at different throughout with different input impedances. Note that all the results for the following graph were taken with a 100-Hz analog input signal and without an ADC driver amplifier.

Design Featured Devices

Link to Key file

Texas Instruments, source files for SBAA256, SBAC178 support files