Input | ADC Input | Digital Output ADS8860 |
---|---|---|
–10V | 0.1V | 0889H or 2185d |
+10V | 2.9V | F777H or 63351d |
Power Supplies | |||
---|---|---|---|
Vref1 | Vref2 | AVDD | DVDD |
1V | 3V | 3V | 3V |
This circuit document describes how to translate a high-voltage signal (for example, ±10V) to low-voltage ADC inputs (for example, 0V to 3V). This circuit does not require any high-voltage supply to operate, but rather uses a voltage divider and level shift to translate the input signal. This circuit shows the OPA365 and ADS8860 devices, but the topology could be applied to many different ADCs. This design can be used a wide range of applications where a high-voltage input needs to be translated such as analog input modules for PLCs, instrumentation (lab, analytical, field and portable), and factory automation and control.
Specification | Goal | Calculated | Simulated |
---|---|---|---|
Sampling rate | 1MSPS (max sampling rate) | 800kSPS | |
Bandwidth | > 1MHz | Poles at 3.39MHz and 4.92MHz | 2.44MHz |
Noise | < 1/2LSB = 38.1µV | 29.52µV | 31.55µV |
Transient settling error | < 1/2LSB = 38.1µV | –2.2µV |
where
Using the values from the calculator:
The following graph shows the linear output response for a –10-V to 10-V input. In this case, the amplifier output is approximately 2.9V for a –10-V input and 0.1V for a +10-V input. This design was scaled so that the output range avoids the nonlinear power supply rails by 0.1V. See the Determining a SAR ADC's Linear Range when using Operational Amplifiers video for detailed theory on this subject.
The bandwidth is limited by the Cf × Rf filter (fc1 = 3.39MHz) and the output filter (fc1 = 4.92MHz). These two poles combine to form a second-order filter with a simulated cutoff frequency at 2.44MHz. See the Op Amps Bandwidth video series for more details on this subject.
The following simulation shows settling to a –10-V DC input signal. This type of simulation shows that the sample and hold kickback filter is properly selected. See the Final SAR ADC Drive Simulations video for detailed theory on this subject. Note: in this example the amplifier had settling issues, so the sampling rate was decreased from 1MSPS to 800kSPS. Reducing the sampling rate increases the acquisition period to improve settling (tacq = 1 / fsamp – tconv = (1/800kSPS) – 710 ns = 540 ns).
The following noise calculation takes into account the thermal noise of the resistor network, the amplifier noise, and the bandwidth limit from the filters. The calculated total noise is 29.52μV and the simulated total noise is 31.55μV. See the Op Amp Noise Calculation video for detailed theory on amplifier noise calculations, and the Calculating the Total Noise for ADC Systems video for data converter noise.
Noise equivalent input resistor network:
Resistor network noise:
OPS365 noise density:
Noise gain:
Total noise:
Device | Key Features | Link | Other Possible Devices |
---|---|---|---|
ADS8860 | 16-bit resolution, SPI, 1-MSPS sample rate, single-ended input, Vref input range 2.5V to 5.0V | 16-bit, 1MSPS, 1-channel SAR ADC with single-ended input, SPI and daisy chain | Precision ADCs |
OPA365 | 50-MHz bandwidth, zero crossover distortion topology, rail-to-rail input and output, noise 4.5nV/√ Hz | 2.2V, 50MHz, Low-Noise, Single-Supply Rail-to-Rail Operational Amplifier | Operational amplifiers (op amps) |
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