SBAA381B April   2019  – May 2024 TLV320ADC3140 , TLV320ADC5140 , TLV320ADC6140

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Processing Blocks of TLV320ADCx140/PCMx140-Q1
    1. 2.1 Decimation Filter Response
      1. 2.1.1 Supported Sample Rates
    2. 2.2 AGC or DRE
      1. 2.2.1 Supported Sample Rates
      2. 2.2.2 Channel Assignment
    3. 2.3 Channel Summer, Digital Mixer, and Bi-quads
  6. 3Processing Blocks Supported for Different Sample Rates
    1. 3.1 8 kHz Sample Rate
    2. 3.2 16 kHz-48 kHz Sample Rate
    3. 3.3 96 kHz Sample Rate
    4. 3.4 192 kHz Sample Rate
    5. 3.5 384 kHz Sample Rate
    6. 3.6 768 kHz Sample Rate
  7. 4Example Configurations
  8. 5References
  9. 6Revision History

4 Example Configurations

A few example device configuration scripts for different combinations are presented below.

Example 1: Two input channels with four output channels using digital mixer.

  1. Differential 2-channel input
  2. Linear phase decimation filter
  3. 24-bit TDM mode
  4. Enable digital mixer mode
  5. Digital Mixer 3: Ch3 Out = 0.5×Ch1 + 0.5×Ch2
  6. Digital Mixer 4: Ch4 Out = 0.5×Ch1 - 0.5×Ch2

# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
#               # ==> comment delimiter
#
# Differential 2-channel 24-bit TDM mode : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW 
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
w 98 00 00 # Goto Page 0
w 98 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
w 98 6B 01          # Linear Phase Decimation Filter with digital mixer 
# Digital Mixer 3 Configuration
w 98 00 04          # Goto Page 4
w 98 28 40 00 00 00 # Digital Mixer 3: Channel 1 Coefficient (MIX3_CH1) = 0.5
w 98 2C 40 00 00 00 # Digital Mixer 3: Channel 2 Coefficient (MIX3_CH2) = 0.5
w 98 30 00 00 00 00 # Digital Mixer 3: Channel 3 Coefficient (MIX3_CH3) = 0.0
w 98 34 00 00 00 00 # Digital Mixer 3: Channel 4 Coefficient (MIX3_CH4) = 0.0
# Digital Mixer 4 Configuration
w 98 00 04          # Goto Page 4
w 98 38 40 00 00 00 # Digital Mixer 4: Channel 1 Coefficient (MIX4_CH1) = 0.5
w 98 3C C0 00 00 00 # Digital Mixer 4: Channel 2 Coefficient (MIX4_CH2) = -0.5
w 98 40 00 00 00 00 # Digital Mixer 4: Channel 3 Coefficient (MIX4_CH3) = 0.0
w 98 44 00 00 00 00 # Digital Mixer 4: Channel 4 Coefficient (MIX4_CH4) = 0.0
 
w 98 00 00 # Goto Page 0
w 98 07 20 # TDM Mode with 24 Bits/Channel
w 98 73 c0 # Enable Ch.1 - Ch.2 
w 98 74 f0 # Enable Ch.1 - Ch.4 ASI Output channels
w 98 75 e0 # Power up ADC

Example 2: Four input channels with channel summer.

  1. Differential 4-channel input
  2. Linear phase decimation filter
  3. 32-bit TDM mode
  4. Two-channel summer mode

# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
#               # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are 
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 4-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2, INP3/INM3 - Ch3 and INP4/INM4 - Ch4
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW 
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
w 98 00 00 # Goto Page 0
w 98 02 81 # Wake-up device by I2C write into P0_R2 using internal AREG
w 98 6B 05 # Linear Phase Filter with 2 channel summer mode (DSP_CFG0)
w 98 00 00 # Goto Page 0
w 98 07 30 # TDM Mode with 32 Bits/Channel
w 98 73 f0 # Enable Ch.1 - Ch.4 
w 98 74 f0 # Enable ASI Output channels
w 98 75 e0 # Power up ADC