SBAA386A December 2019 – September 2024 ADS125H02 , MUX509
Feature | Value | Units |
---|---|---|
Number of channels | 4 | Differential channels |
Data rate | ≤10 | kSPS |
Voltage input range | ±10.0 | Volts |
Current input range | 0 to 20 | mA |
Voltage accuracy | 0.05 typical | 0.10 maximum | %FS |
Current accuracy | 0.10 typical | 0.20 maximum | %FS |
AVDD | HV-AVDD | HV-AVSS |
---|---|---|
5.0V | 15.0V | –15.0V |
This circuit design describes how to use an ADS125H02 with integrated reference and programmable gain amplifier (PGA) to make voltage and current measurements on various ranges.
This circuit can be used in applications such as
Thermocouples and RTD are also common temperature sensors used in similar applications. For more information about making precision ADC measurements with a variety of RTD wiring configurations, see the A Basic Guide to Thermocouple Measurements Application Report.
Specification | Data Sheet Value | Error (ppm) Including ΔT = 90°C |
Error (ppm) Assuming Gain and Offset Calibration |
---|---|---|---|
Internal VREF initial accuracy (maximum) | 0.20% | 2000.000 | 1.325 |
Internal VREF temperature drift (maximum) | 1ppm/°C | 90.000 | 90.000 |
Internal VREF temperature hysteresis (70 ppm/105°C) | 60ppm/°C | 60.000 | 60.000 |
Quantization noise | 172.3nVRMS | 0.017 | 0.017 |
Noise | 53μVRMS | 5.300 | 5.300 |
INL | 0.001% | 10.000 | 10.000 |
Offset | 2500μV | 250.000 | 1.325 |
Offset temperature drift | 2000nV/°C | 18.000 | 18.000 |
Gain error | 0.70% | 7000.000 | 1.325 |
Gain error temperature drift | 4ppm/°C | 360.000 | 360.000 |
Total error (root sum of squares) [ppm] | 7294.124 | 376.507 | |
Total error (root sum of squares) [%FS] | 0.729 | 0.038 |
where
In both the voltage and current measurements, since the gain < 1, the absolute input voltage must be:
The following image shows the relationship between the PGA input voltage to the PGA output voltage in attenuation mode. The first PGA stage is configured as a unity-gain follower, the second PGA stage attenuates the differential input and shifts the signal common-mode voltage to AVDD / 2 to drive the ADC input.
The ADS125H02 device provides four GPIO pins (GPIO0–GPIO4), two GPIOs are available on dedicated pins and two GPIOs are multiplexed functions with an external reference (REFP1 and REFN1). The GPIO input and output levels are referred to AVDD and AGND, so in this case the logic output levels are set to 5.0V. The following bits in registers 3 and 4 are used to control the GPIOs:
In this case, set GPIO_CON[3:0] to '0111', and set GPIO_DIR[3:0] to '1000', while the configuration for GPIO_DAT[3:0] are dependent upon the connected channel. The MUX509 Truth Table and GPIO_DAT Configuration table shows the configuration of the individual GPIO[x] bits depending on the input channel selected.
EN | GPIO2 | A1 | GPIO1 | A0 | GPIO0 | State |
---|---|---|---|
0 | 1 | 1 | MUX disabled |
1 | 0 | 0 | Channel 1 ON (Voltage) |
1 | 0 | 1 | Channel 2 ON (Voltage) |
1 | 1 | 0 | Channel 3 ON (Current) |
1 | 1 | 1 | Channel 4 ON (Current) |
Digital low-pass filters are essential to the functionality of a delta-sigma ADC, which relies on oversampling and noise shaping to push quantization noise out of band. There are a variety of options for digital filters available in the ADS125H02 device. When choosing a digital filter, consider the following tradeoffs:
In this application, TI recommends a low-latency 20SPS using a SINC1 filter, which is shown in the pseudocode example in the following section.
For more information about digital filters in the ADS125H02 device, see the following:
Register Address | Register Name | Field | Register Value | Description |
---|---|---|---|---|
05h | MODE3 | GPIO_DAT[3:0] | See MUX509 Truth Table and GPIO_DAT Configuration | GPIO state (to control the external MUX) |
MODE2 | GPIO_DIR[3:0] | 1000 |
GPIO[2:0] outputs, GPIO[3] input |
|
MODE4 | GPIO_CON[3:0] | 0111 |
GPI0[2:0] connected GPIO[3] disconnected |
|
10h | MODE4 | MUX[2:0] | 000 | Internal MUX |
10h | MODE4 | GAIN[3:0] | 0010 or 0011 | PGA - Gains for voltage and current measurements, respectively |
02h | MODE0 | DR[4:0] | 00100 | Data rate: 20SPS |
02h | MODE0 | FILTER[2:0] | 000 | Digital filter: SINC1 |
The following pseudocode sequence shows the required steps to set up the device and the microcontroller that interfaces to the ADC to take subsequent readings from the ADS125H0x device for both voltage and current measurements. The dedicated DRDY pin indicates the availability of new conversion data. Pseudocode is shown without the use of the STATUS byte and CRC data verification. Download the ADS125H02 Example C Code from the ADS125H02 product folder or access it directly with the following link: ADS125H02 Example C Code.
Generic Pseudocode
Init:
{
Configure microcontroller for SPI master, mode 1 (CPOL = 0, CPHA = 1), SCLK freq = 8 MHz
Configure microcontroller GPIO for /DRDY as a falling edge triggered interrupt input
Set CS1 low;
Send 06h 00h A9h 00h;// RESET command to ensure proper reset after power-up
Set CS1 high;
// DELAY
Set CS1 low;
Send 46h 10h 82h 00h;// WREG to REF: Enable and select the internal 2.5V reference
Set CS1 high;
// NOTE: not necessary to issue a WREG to MODE0 command when using the default register values
Set CS1 low;
Send 42h 24h 5Ah 00h;// WREG to MODE0: Continuous conversion, low-latency filter, 20 SPS
Set CS1 high;
Set CS1 low;
Send 43h 08h 8Bh 00h;// WREG to MODE1: Continuous conversion, 605us conv. start delay
Set CS1 high;
Set CS1 low;
Send 44h 77h 9Ah 00h;// WREG to MODE2: Enable GPIO outputs on GPIO0, GPIO1, and GPIO2
Set CS1 high;
Set channelNumber = 1
Call Gain_Select()
Call Channel_Select()
// (OPTIONAL): For verification read back all register settings
Call Start_New_Conversion()
}
Loop:
{
Wait for DRDY falling edge interrupt...
Do you want to switch to the next channel?
{
channelNumber = (channelNumber + 1) % 4;
Call Gain_Select()
Call Channel_Select()
Call Start_New_Conversion()
}
Call Read_Data()
}
Channel_Select()
{
// NOTE:
// A0, A0 and EN are controlled by GPIO0, GPIO1 and GPIO2 respectively
// STATUS0 byte is always enabled
Set CS1 low;
// WREG to MODE3 register to set GPIO pin levels
If (channelNumber == 1)
Send 45h 44h 16h 00h;// EN=1; A1=A0=0
ElseIf (channelNumber == 2)
Send 45h 45h 11h 00h;// EN=1; A1=0; A0=1
ElseIf (channelNumber == 3)
Send 45h 46h 18h 00h;// EN=1; A1=1; A0=0
ElseIf (channelNumber == 4)
Send 45h 47h 1Fh 00h;// EN=1; A1=A0=1
Set CS1 high;
}
Gain_Select()
{
// NOTE:
// Using gain of 0.25 V/V for channels 1 & 2
// Using gain of 0.50 V/V for channels 3 & 4
// Always select AINP = AIN1 and AINN = AIN0 for analog inputs
Set CS2 low;
// WREG to MODE4 register to configure PGA gain
If (channelNumber <= 2)
Send 50h 02h D5h 00h;// Gain = 0.25 V/V
Else
Send 50h 03h D2h 00h;// Gain = 0.50 V/V
Set CS2 high;
}
Start_New_Conversion()
{
Set CS1 low;
Send 08h 00h 7Fh 00h;// START command
Set CS1 high;
}
Read_Data()
{
Set CS1 low;
Send 12h 00h AAh 00h 00h 00h 00h 00h 00h;
Receive FFh 12h 00h AAh [STATUS] [MSB] [MID] [LSB] [CRC]
Set CS1 high;
// Cast, concatenate, and sign-extend 24-bit data to signed 32-bit datatype
signedValue = (((int32_t) [MSB] << 24) + ((int32_t) [MID] << 16) + ((int32_t) [LSB] << 8)) >> 8;
// Convert ADC value to voltage (LSBsize = 2*VREF/GAIN)
// NOTE:
// Using gain of 0.25 V/V for channels 1 & 2
// Using gain of 0.50 V/V for channels 3 & 4
VoltageReading = (LSBsize * signedValue);
If (channelNumber > 2)
CurrentReading = (VoltageReading / BurdenResistance);
}
Device | Key Features | Link | Other Possible Devices |
---|---|---|---|
Analog to Digital Converter (ADC) with Integrated PGA and Voltage Reference | |||
ADS125H02 | 24-bit, 40kSPS, 2-channel delta-sigma ADC with ±20-V input, PGA, IDACs, GPIOs, and VREF | 24 bit, 40kSPS, 2-ch delta-sigma ADC with ±20-V input, PGA, IDACs, GPIOs and VREF | Precision ADCs |
ADS125H01 | 24-bit, 40kSPS, 1-channel delta-sigma ADC with ±20-mV to ±20-V input | 24 bit, 40kSPS, 1-ch delta-sigma ADC with low-noise PGA and ±20-V input | |
Programmable Gain Amplifier (PGA) | |||
PGA280 | 4-channel, zero-drift, high voltage, programmable gain amplifier (PGA) | Zero Drift, HV Programmable Gain Amplifier | Analog switches and muxes |
PGA281 | 1-channel, zero-drift, high voltage, programmable gain amplifier (PGA) | Zero-Drift, High Voltage Programmable Gain Amplifier | |
Analog Multiplexer | |||
MUX509 | Differential or dual 4:1, 36.0-V, precision analog multiplexer | 6.7-pF on-state capacitance, 36V, 4:1, 2-channel analog multiplexer | Analog switches and muxes |
MUX36D04 |
Differential or dual 4:1, 36.0-V, precision analog multiplexer Lower leakage current |
1-pA on-state leakage current, 36V, 4:1, 2-channel precision analog multiplexer | |
TMUX6104 |
Single-ended 4:1, ±16.5-V, precision analog multiplexer Lowest leakage current, lowest on-capacitance |
5-pA on-state leakage current, ±16.5V, 4:1, 1-channel precision analog multiplexer | |
CD4052 |
Differential or dual 4:1, ±10.0-V analog multiplexer Lowest cost |
20V, 4:1, 2-channel general-purpose multiplexer |
The ADS125H02 device requires three analog power supplies (high-voltage supplies HV_AVDD and HV_AVSS, and low-voltage analog supply AVDD) and a digital power supply (DVDD). This circuit assumes a bipolar supply (±15.0V) for HV_AVDD and HV_AVSS, and a 5.0-V supply. The following table shows there are specifications for three reference designs that can provide the power supplies from a 24.0-V nominal input voltage.
PMP10532 | PMP10516 | TIDA-00689 | ||
---|---|---|---|---|
VIN range (V) | 19.0–30.0V | 20.4–28.8V | 16.0–32.0V | |
Input type | DC | |||
VOUT (V) | Output 1 | 15.0 | ||
Output 2 | –15.0 | |||
Output 3 | 5.00 | |||
IOUT(maximum) (A) | Output 1 | 0.200 | 0.200 | 0.601 |
Output 2 | 0.200 | 0.060 | 0.601 | |
Output 3 | 1.000 | 0.100 | 0.200 | |
POUT(maximum) (W) | Output 1 | 3.0 | 3.0 | 0.5 |
Output 2 | 3.0 | 0.9 | ||
Output 3 | 5.0 | 0.5 | ||
Isolation | ✔ | ✔ | ✔ | |
Total efficiency at VIN = 24V and Maximum IOUT | 86.0% | 78.8% | 44.0% | |
Footprint | 60.0mm × 30.0mm | Approximately 60.0mm × 35.0mm | 12.7mm × 40.8mm | |
Topology | Fly-Buck™ | Fly-Buck™ + Linear regulator | Fly-Buck™ + Split rail converter |