SBAA400A September   2019  – December 2023 PCM5140-Q1 , PCM6140-Q1 , TLV320ADC5140 , TLV320ADC6140

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Dynamic Range Enhancer
    1. 2.1 High Pass Filter
    2. 2.2 DRE Parameters
    3. 2.3 Sample Rate Support
  6. 3Example
  7. 4References
  8. 5Revision History

2.2 DRE Parameters

Table 2-3 show the parameters of the DRE algorithm. Two of the parameters are controlled by writing to the device registers. The other parameters reside in the 32-bits wide coefficient memory (Book 0, Page 5, Page 6, and Page 7) of the device.

Table 2-3 List of DRE Parameters
DRE PARAMETERFUNCTION/DESCRIPTION
DRE threshold (dB)The signal level above which the DRE is inactive.
Maximum Gain (dB)Upper limit of gain applied by DRE.
Release Time Constant (seconds)How fast the DRE circuitry responds with a PGA gain increase when the input signal falls below DRE threshold.
Attack Time Constant (seconds)How fast the DRE circuitry responds with a PGA gain decrease when the input signal rises above DRE threshold.
Release Hysteresis (dB)Amount of signal-level decrease in dB past the DRE threshold that forces the DRE to increase gain and start a release.
Attack Hysteresis (dB)Amount of signal-level increase in dB past the DRE threshold that forces the DRE to decrease gain and start an attack.
Release Debounce (samples)The number of consecutive input samples that falls below the DRE threshold after an attack event before the DRE starts a release and increases the PGA gain.
Attack Debounce (samples)The number of consecutive input samples that rises above the DRE threshold after a release event before the DRE starts an attack and decreases the PGA gain.

DRE threshold: The signal level above which the DRE stops modifying the PGA and sets it to unity gain. The threshold level is expressed relative to full scale (dBFS) of the ADC output. Table 2-4 lists the DRE threshold configuration settings. The default is -54 dB. Setting a high threshold level reduces the headroom available for the DRE to react when there is a sudden increase in the signal level and can result in digital clipping and PGA saturation. Therefore, the DRE threshold has to be set with enough margin to prevent clipping with large dynamic changes in input levels.

Table 2-4 DRE Trigger Threshold Level Programmable Settings
P0_R109_D[7:4] : DRE_LVL[3:0]DRE TRIGGER THRESHOLD LEVEL
0000The DRE target threshold is the –12 dB output signal level.
0001The DRE target threshold is the –18 dB output signal level.
0010The DRE target threshold is the –24 dB output signal level.
……
0111 (default)The DRE target threshold is the –54 dB output signal level.
……
1001The DRE target threshold is the –66 dB output signal level.
1010 to 1111Reserved (do no use these settings)

Maximum Gain: The maximum gain represents the upper limit of gain applied by the DRE for signals below the DRE threshold. Table 2-5 lists the Maximum Gain configuration settings. The default value is 24 dB. It can be programmed from 2 dB to 30 dB with steps of 2 dB.

Table 2-5 DRE Maximum Gain Programmable Settings
P0_R109_D[3:0] : DRE_MAXGAIN[3:0]DRE MAXIMUM GAIN ALLOWED
0000The DRE maximum gain allowed is 2 dB.
0001The DRE maximum gain allowed is 4 dB.
0010The DRE maximum gain allowed is 6 dB.
……
1011 (default)The DRE maximum gain allowed is 24 dB.
……
1110The DRE maximum gain allowed is 30 dB.
1111Reserved (do not use this setting)

Release Time Constant: How fast the DRE circuitry increases the PGA gain when the input signal falls below the DRE threshold. The Release Time Constant is controlled by two coefficients:DRE_REL_ALPHA and DRE_REL_BETA. Equation 5 and Equation 6 show how to compute the DRE_REL_ALPHA and DRE_REL_BETA parameters from the following time constant.

Equation 5. GUID-516116DA-8D59-4927-B578-845E20F83A9E-low.gif
Equation 6. GUID-8AB8D80B-6570-4766-92B2-ECEE852DC8C9-low.gif

where

  • RT is the Release Time Constant in seconds
  • FSYNC is the sample rate of the ADC in Hz

Table 2-6 shows the registers that control the DRE_REL_ALPHA and DRE_REL_BETA parameters. Theses parameters are each 32-bits wide, and have to be written in 2s-complement representation. The default values for DRE_REL_ALPHA and DRE_REL_BETA corresponds to a time constant of 20 milliseconds.

Table 2-6 Programmable Registers for Release Time Constant Parameter
COEFFICIENTPAGEREGISTERRESET VALUEDESCRIPTION
DRE_REL_ALPHA0x050x7C0x7FDRE_REL_ALPHA Byte[31:24]
0x050x7D0xB5DRE_REL_ALPHA Byte[23:16]
0x050x7E0x16DRE_REL_ALPHA Byte[15:8]
0x050x7F0x50DRE_REL_ALPHA Byte[7:0]
DRE_REL_BETA0x060x080x00DRE_REL_BETA Byte[31:24]
0x060x090x4ADRE_REL_BETA Byte[23:16]
0x060x0A0xE9DRE_REL_BETA Byte[15:8]
0x060x0B0xB0DRE_REL_BETA Byte[7:0]

Attack Time Constant: How fast the DRE circuitry decreases the PGA gain when input signal rises above the DRE threshold. The Attack Time Constant is controlled by two coefficients: DRE_ATT_ALPHA and DRE_ATT_BETA. Equation 7 and Equation 8 show how to compute the DRE_ATT_ALPHA and DRE_ATT_BETA parameters from the following time constant.

Equation 7. GUID-331A2097-E2AD-4528-AD0A-68398F92FBFF-low.gif
Equation 8. GUID-5836DCE4-E1E3-4ADA-92EC-72D241F1F118-low.gif

where

  • AT is the Attack Time Constant in seconds
  • FSYNC is the sample rate of the ADC in Hz

DRE_ATT_ALPHA and DRE_ATT_BETA coefficients are each 32-bits wide, 2s-complement representations. Table 2-7 shows the registers that control DRE_ATT_ALPHA and DRE_ATT_BETA parameters. The default values for DRE_ATT_ALPHA and DRE_ATT_BETA corresponds to a time constant of 0.1 milliseconds.

Table 2-7 Programmable Registers for Attack Time Constant Parameter
COEFFICIENTPAGEREGISTERRESET VALUEDESCRIPTION
DRE_ATT_ALPHA0x060x0C0x50DRE_ATT_ALPHA Byte[31:24]
0x060x0D0xFCDRE_ATT_ALPHA Byte[23:16]
0x060x0E0x64DRE_ATT_ALPHA Byte[15:8]
0x060x0F0x5CDRE_ATT_ALPHA Byte[7:0]
DRE_ATT_BETA0x060x100x2FDRE_ATT_BETA Byte[31:24]
0x060x110x03DRE_ATT_BETA Byte[23:16]
0x060x120x9BDRE_ATT_BETA Byte[15:8]
0x060x130xA4DRE_ATT_BETA Byte[7:0]

Release Hysteresis: Amount of signal-level decrease past the DRE threshold that forces the DRE to increase gain and start a release. Release Hysteresis is specified in dB. Equation 9 shows the computation of the DRE_REL_HYST parameter.

Equation 9. GUID-33E85E9D-02FE-4367-8287-BD99AF093FD7-low.gif

where

  • RH (>= 0) is the Release Hysteresis in dB

The default value of DRE_REL_HYST is 0x00000300, which corresponds to a hysteresis of 3 dB. Table 2-8 shows the registers that control the DRE_REL_HYST parameter.

Table 2-8 Programmable Registers for Release Hysteresis Parameter
COEFFICIENTPAGEREGISTERRESET VALUEDESCRIPTION
DRE_REL_HYST0x060x340x00DRE_REL_HYST Byte[31:24]
0x060x350x00DRE_REL_HYST Byte[23:16]
0x060x360x03DRE_REL_HYST Byte[15:8]
0x060x370x00DRE_REL_HYST Byte[7:0]

Attack Hysteresis: Amount of signal-level increase past DRE threshold that forces the DRE to decrease the gain and start an attack. Equation 10 shows the computation of the DRE_ATT_HYST parameter.

Equation 10. GUID-BC2E45CD-BB6B-415F-9667-2D144A7CB7FC-low.gif

where

  • AH (>= 0) is the Attack Hysteresis in dB

The default value of Attack Hysteresis is 1 dB. The default can be changed by writing to the registers listed in Table 2-9.

Table 2-9 Programmable Registers for Attack Hysteresis Parameter
COEFFICIENTPAGEREGISTERRESET VALUEDESCRIPTION
DRE_ATT_HYST0x060x3C0x00DRE_ATT_HYST Byte[31:24]
0x060x3D0x00DRE_ATT_HYST Byte[23:16]
0x060x3E0x01DRE_ATT_HYST Byte[15:8]
0x060x3F0x00DRE_ATT_HYST Byte[7:0]

Attack Debounce: The number of consecutive input samples that rises above the DRE threshold after a release event before the DRE starts attack and decreases the PGA. The default value of this parameter is 2 samples at 48 kHz (0.01 milliseconds). Equation 11 shows the computation of DRE_ATT_CNT parameter.

Equation 11. GUID-E38D2D12-54F1-40F1-850A-5B2A29700319-low.gif

where

  • AD (>= 0) is specified in seconds
  • FSYNC is the sample rate of the ADC in Hz

Table 2-10 shows the registers controlling the DRE_ATT_CNT parameter.

Table 2-10 Programmable Registers for Attack Debounce Parameter
COEFFICIENTPAGEREGISTERRESET VALUEDESCRIPTION
DRE_ATT_CNT0x060x180x00DRE_ATT_CNT Byte[31:24]
0x060x190x00DRE_ATT_CNT Byte[23:16]
0x060x1A0x02DRE_ATT_CNT Byte[15:8]
0x060x1B0x00DRE_ATT_CNT Byte[7:0]

Release Debounce: The number of consecutive input samples that falls below DRE threshold after an attack event before the DRE starts releasing and increasing the PGA. The default value of Release Debounce is 25 milliseconds at 48 kHz. Equation 12 shows the computation of the DRE_REL_CNT parameter.

Equation 12. GUID-8CA68E39-8322-41FB-AAAE-771C9B33F68A-low.gif

where

  • RD (>= 0) is the Release Debounce specified in seconds
  • FSYNC is the sample rate of the ADC in Hz

Table 2-11 lists the registers controlling the DRE_REL_CNT parameter.

Table 2-11 Programmable Registers for Release Debounce Parameter
COEFFICIENTPAGEREGISTERRESET VALUEDESCRIPTION
DRE_REL_CNT0x060x1C0x00DRE_REL_CNT Byte[31:24]
0x060x1D0x04DRE_REL_CNT Byte[23:16]
0x060x1E0xB0DRE_REL_CNT Byte[15:8]
0x060x1F0x00DRE_REL_CNT Byte[7:0]