Reducing Phase Delay by Averaging on ADS8686S with Burst Sequencer Mode
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1 Introduction
In a grid infrastructure application, measuring the phase difference between different signals is critical to ensure the safety of the power grid. The simultaneous sampling, multiple-channels inputs analog-to-digital converter (ADC) is ideal for the kind of application. However, to reduce the channel count and the cost, a non-simultaneous sampling, multiple-channels inputs ADC with internal multiplexer can be used.
When multiple input channels are sampled in a sequential manner as in a multiplexed ADC, an additional phase delay is introduced between the channels because of channel switching. The measured phase value of the signal includes this additional phase delay which is not expected by the design engineer and will lead to an inaccurate phase difference measurement. The reference design of Phase-Compensated, 8-Ch, Multiplexed Data Acquisition System for Power Automation Reference Design introduces a method how to compensate the additional phase delay caused by the channel switching on the internal multiplexer.
ADS8686S is a 16-channel, 16-bit, 1Msps, Dual simultaneous sampling successive approximation register (SAR) based ADC, the integrated analog front-end (AFE) with 1MΩ input impedance eliminates the requirement of ADC driver. The 16-channel inputs can meet the requirement in most multi-phase power measurement systems and make it possible to design a compact system. However, the channel switching on each ADC A/B of ADS8686S will introduce an additional phase delay.
Figure 1-1 Typical Application Circuit Using
ADS8686S in Grid Infrastructure System2 Phase Delay and Non-Simultaneous Sampling
The terminology non-simultaneous sampling suggests that all input channels of a multi-channel system are not sampled at the same time instant by the ADC. This limitation is very typical in the case of a multiplexed input ADC, as the converter sequentially scans through the multiple input channels. An example of two alternating signals such as a voltage (V) and a current (I) is shown in Figure 2-1.
Figure 2-1 Phase Delay between Sinusoidal
WaveformsTo only consider the phase delay between two channels due to the ADC’s channel switching, we assume that the initial phase angle and the frequencies of these two signals are exactly same. The conversion cycle time of the ADC is Ts (inverse of sampling frequency fs), so the additional time delay between two consecutive channels is Ts.
If the initial phase angle of two signals applied to different channels of a non-simultaneous sampling ADC is zero, then the theoretical additional phase delay in degree between the two consecutive channels can be calculated below:
Where, fin is the signal frequency of input periodic signal (fin=1/Tin), fadc is the sampling frequency for ADC ( fs=1/Ts), 360° is the phase angle of a full cycle. Note that one degree is equal to 60 minutes of arc (arcminute) or 3600 seconds of arc (arcminute).
When ADS8686S operates on its maximum sampling frequency 1MHz and two 50Hz sinusoidal signals with the same initial phase angle are applied to two consecutive channels, the theoretical phase delay is:
If all 8 channels on one ADC of ADS8686S are selected and used, the maximum phase delay in theory between first (1st) and last (8th) channel is:
This phase delay is equal to one complete conversion cycle of the ADC and hence, while such multiplexed systems introduce an additional phase delay between the input channels, the value of this phase delay is deterministic and small if the ADS8686S operates at a fast sampling rate.
