SBAA487 January   2021 ADS8664 , ADS8668 , ADS8674 , ADS8678 , ADS8684 , ADS8684A , ADS8686S , ADS8688 , ADS8688A , ADS8694 , ADS8698

 

  1.   Trademarks
  2. 1Introduction
  3. 2Phase Delay and Non-Simultaneous Sampling
  4. 3Averaging with Sequencer and Burst Sequencer mode
    1. 3.1 Averaging with Sequencer
    2. 3.2 Averaging with Burst Sequencer
  5. 4Verification and Measured Result
    1. 4.1 Phase Delay Measurement
      1. 4.1.1 Measured Phase Delay without Averaging – 50Hz Sinusoidal Fundamental Signal
      2. 4.1.2 Measured Phase Delay with Averaging – 50Hz sinusoidal fundamental signal
      3. 4.1.3 Comparison
    2. 4.2 AC Performance
  6. 5Summary
  7. 6References

2 Phase Delay and Non-Simultaneous Sampling

The terminology non-simultaneous sampling suggests that all input channels of a multi-channel system are not sampled at the same time instant by the ADC. This limitation is very typical in the case of a multiplexed input ADC, as the converter sequentially scans through the multiple input channels. An example of two alternating signals such as a voltage (V) and a current (I) is shown in Figure 2-1.

GUID-20210106-CA0I-X5KJ-RVFX-40XQ4Z6CHTJX-low.gif Figure 2-1 Phase Delay between Sinusoidal Waveforms

To only consider the phase delay between two channels due to the ADC’s channel switching, we assume that the initial phase angle and the frequencies of these two signals are exactly same. The conversion cycle time of the ADC is Ts (inverse of sampling frequency fs), so the additional time delay between two consecutive channels is Ts.

If the initial phase angle of two signals applied to different channels of a non-simultaneous sampling ADC is zero, then the theoretical additional phase delay in degree between the two consecutive channels can be calculated below:

Equation 1. GUID-20210106-CA0I-P6QX-2HL3-XKN9PF7F2TQP-low.gif

Where, fin is the signal frequency of input periodic signal (fin=1/Tin), fadc is the sampling frequency for ADC ( fs=1/Ts), 360° is the phase angle of a full cycle. Note that one degree is equal to 60 minutes of arc (arcminute) or 3600 seconds of arc (arcminute).

When ADS8686S operates on its maximum sampling frequency 1MHz and two 50Hz sinusoidal signals with the same initial phase angle are applied to two consecutive channels, the theoretical phase delay is:

Equation 2. GUID-20210106-CA0I-WBBF-HCDZ-8XKBF88JBX2Q-low.gif

If all 8 channels on one ADC of ADS8686S are selected and used, the maximum phase delay in theory between first (1st) and last (8th) channel is:

Equation 3. GUID-20210106-CA0I-HDMZ-1LTN-PP949TG1WVW6-low.gif

This phase delay is equal to one complete conversion cycle of the ADC and hence, while such multiplexed systems introduce an additional phase delay between the input channels, the value of this phase delay is deterministic and small if the ADS8686S operates at a fast sampling rate.