SBAA491A November 2021 – April 2022 PCM5120-Q1 , PCM6120-Q1 , TLV320ADC5120 , TLV320ADC6120
The DRC algorithm is a mixed-signal solution, where the analog programmable gain amplifier (PGA) of a channel is controlled by a closed-loop control digital algorithm. Figure 2-1 shows the signal processing chain for the device. To respond to changes in the input signal, the DRC algorithm monitors the digitized signal from the ADC and adjusts the PGA to maintain a constant target level below a certain threshold. If the signal is below the threshold level, the DRC increases the PGA gain. If the signal is above the threshold level, the DRC keeps the default PGA gain. Using the analog circuitry of the PGA to change the input signal provides optimal noise performance, since it avoids gain adjustments in the digital circuitry that increases the quantization noise. Moreover, the DRC algorithm uses a small step size during PGA changes to reduce distortions in the input signal. As shown in DRC Selection Using DSP_CFG1 Register, DRC selection is done using the DRE_AGC_SEL and DRC_EN bits of DSP_CFG1 register (page = 0x00, address = 0x6C).
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 3 | DRE_AGC_SEL | R/W | 0b | DRE or DRE
selection when is enabled for any channel. 0d = DRE is selected. 1d = DRE is selected. |
| 1 | DRC_EN | R/W | 0b | Dynamic range
compression (DRC) same as DRE without gain compesnation in
digital 0d = DRC disabled. Device can be in DRE or AGC mode depending on DRE_AGC_SEL bit. 1d = DRC enabled. Device cannot be in DRE or AGC mode. |
DRE/DRC can be independently enabled or disabled for each channel using the following register bits: