SBAA493A June 2021 – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

2 Target Mode Power Consumption With PLL Enabled

Table 2-1 describes the typical current consumption of the TLV320ADCx120/PCMx120-Q1 when the PLL is enabled with AVDD set to 1.8 V and 3.3 V. The PLL is enabled by:

Setting the bit field PLL_PDZ in the PWR_CFG register
Applying a FSYNC and BCLK with the desired sampling rate and BCLK to FSYNC ratio

In this table, when the DRE was enabled, the DRE threshold was set to –36 dB. The current consumption measurements had the Biquad Filters disabled and inputs grounded.

Table 2-1 Typical Current Consumption (PLL Enabled)

SAMPLING FREQUENCY (kHz)	ADC CHANNELS	DRE	DECIMATION FILTERS	BCLK RATIO	WORD LENGTH	AVDD CURRENT AT 3.3 V (mA)	AVDD CURRENT AT 1.8 V (mA)
8	1	Disabled	Linear Phase	32	32	7.66	7.34
	2			48	24	11.52	10.92
	2			96	24	11.56	10.95
16	1	Disabled	Linear Phase	24	24	7.84	7.56
	1		Low Latency	24		7.91	7.63
	2		Linear Phase	48		11.88	11.26
			Low Latency	48		12.02	11.41
			Linear Phase	96		11.88	11.27
			Low Latency	96		12.02	11.41
	1	Enabled	Linear Phase	24		8.11	7.84
	1		Low Latency	24		8.19	7.91
	2		Linear Phase	48		12.43	11.82
			Low Latency	48		12.57	11.95
			Linear Phase	96		12.43	11.82
			Low Latency	96		12.57	11.96
24	1	Disabled	Linear Phase	24	24	7.98	7.70
	1		Low Latency	24		8.12	7.84
	2		Linear Phase	48		12.08	11.47
			Low Latency	48		12.36	11.73
			Linear Phase	96		12.08	11.46
			Low Latency	96		12.36	11.75
	1	Enabled	Linear Phase	24		8.31	8.03
	1		Low Latency	24		8.46	8.17
	2		Linear Phase	48		12.84	12.23
			Low Latency	48		13.13	12.51
			Linear Phase	96		12.84	12.22
			Low Latency	96		13.12	12.51
32	1	Disabled	Linear Phase	24	24	8.10	7.82
	1		Low Latency	24		8.10	7.82
	2		Linear Phase	48		12.27	11.66
			Low Latency	48		12.27	11.65
			Linear Phase	96		12.25	11.67
			Low Latency	96		12.28	11.66
	1	Enabled	Linear Phase	24		8.49	8.21
	1		Low Latency	24		8.49	8.21
	2		Linear Phase	48		13.16	12.53
			Low Latency	48		13.15	12.53
			Linear Phase	96		13.17	12.54
			Low Latency	96		13.16	12.54
48	1	Disabled	Linear Phase	24	24	8.39	8.10
	1		Low Latency	24		8.29	8.01
	2		Linear Phase	48		12.78	12.16
			Low Latency	48		12.59	11.97
			Linear Phase	96		12.81	12.19
			Low Latency	96		12.62	12.00
	1	Enabled	Linear Phase	24		8.90	8.61
	1		Low Latency	24		8.81	8.52
	2		Linear Phase	48		14.18	13.55
			Low Latency	48		13.99	13.37
			Linear Phase	96		14.21	13.59
			Low Latency	96		14.03	13.40
96	1	Disabled	Linear Phase	24	24	9.45	9.16
	1		Low Latency	24		9.26	8.97
	2		Linear Phase	48		15.15	14.51
			Low Latency	48		14.75	14.12
			Linear Phase	96		15.23	14.59
			Low Latency	96		14.83	14.20
	1	Enabled	Linear Phase	24		10.47	10.18
	1		Low Latency	24		10.27	9.98
	2		Linear Phase	48		17.13	16.49
	2		Low Latency	48		16.74	16.10
192	1	Disabled	Linear Phase	24	24	9.96	9.67
	1		Low Latency	24		11.13	10.84
	2		Linear Phase	48		15.80	15.16
			Low Latency	48		18.12	17.47
			Linear Phase	96		15.97	15.35
			Low Latency	96		18.07	17.66
	1	Enabled	Linear Phase	24		11.69	11.39
	1	Enabled	Low Latency	24		13.16	12.86
384	1	Disabled	Linear Phase	24	24	11.53	11.24