SBAA494A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2. 1Introduction
  3. 2Processing Blocks of TLV320ADCx120 and PCMx120-Q1
    1. 2.1 Decimation Filter Response
      1. 2.1.1 Supported Sample Rates
    2. 2.2 AGC, DRE, or DRC
      1. 2.2.1 Supported Sample Rates
      2. 2.2.2 Channel Assignment
    3. 2.3 Channel Summer, Digital Mixer, and Bi-quads
  4. 3Processing Blocks Supported for Different Sample Rates
    1. 3.1 8 kHz Sample Rate
    2. 3.2 16 kHz-48 kHz Sample Rate
    3. 3.3 96 kHz Sample Rate
    4. 3.4 192 kHz Sample Rate
    5. 3.5 384 kHz Sample Rate
    6. 3.6 768 kHz Sample Rate
  5. 4Example Configurations
  6. 5Related Documentation
  7.   A Revision History

1 TLV320ADCx120 and PCMx120-Q1 Sampling Rates and Programmable Processing Blocks Supported

This application report describes the available processing blocks in the decimation filter chain of the TLV320ADCx120 and PCMx120-Q1 family of devices. The document also explains the supported configurations of the various processing blocks as a function of the sample rate and number of channels.