SBAA494A May   2021  – April 2022 PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2. 1Introduction
  3. 2Processing Blocks of TLV320ADCx120 and PCMx120-Q1
    1. 2.1 Decimation Filter Response
      1. 2.1.1 Supported Sample Rates
    2. 2.2 AGC, DRE, or DRC
      1. 2.2.1 Supported Sample Rates
      2. 2.2.2 Channel Assignment
    3. 2.3 Channel Summer, Digital Mixer, and Bi-quads
  4. 3Processing Blocks Supported for Different Sample Rates
    1. 3.1 8 kHz Sample Rate
    2. 3.2 16 kHz-48 kHz Sample Rate
    3. 3.3 96 kHz Sample Rate
    4. 3.4 192 kHz Sample Rate
    5. 3.5 384 kHz Sample Rate
    6. 3.6 768 kHz Sample Rate
  5. 4Example Configurations
  6. 5Related Documentation
  7.   A Revision History

2.1 Decimation Filter Response

The decimation filter processes the oversampled data from either the multi-bit delta-sigma modulator of the analog channels or the oversampled PDM stream from the digital microphones, and generates the output PCM samples at the output sample rate or frame synchronization (FSYNC) rate. The decimation filter option is selected by configuring the DECI_FILT, P0_R107_D[5:4] register bits. Table 2-1 shows the configuration register setting for the decimation filter mode selection for the record channel. It supports three options: linear phase, low latency, or ultra-low latency decimation filters.

Table 2-1 Decimation Filter Mode Selection for the Record Channel
P0_R107_D[5:4] : DECI_FILT[1:0]DECIMATION FILTER MODE SELECTION
00 (default)Linear phase decimation filters
01Low-latency approximately linear phase decimation filters
10Ultra-low latency decimation filters
11Reserved